參數(shù)資料
型號(hào): PI7C8150BNDIE
廠商: Pericom
文件頁數(shù): 89/109頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 80 of 109
April 2009 – Revision 1.08
14.1.10
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h
Bit
Function
Type
Description
7:0
Primary Bus
Number
R/W
Indicates the number of the PCI bus to which the primary interface
is connected. The value is set in software during configuration.
Reset to 0
14.1.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
Bit
Function
Type
Description
15:8
Secondary Bus
Number
R/W
Indicates the number of the PCI bus to which the secondary
interface is connected. The value is set in software during
configuration.
Reset to 0
14.1.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
Bit
Function
Type
Description
23:16
Subordinate Bus
Number
R/W
Indicates the number of the PCI bus with the highest number that is
subordinate to the bridge. The value is set in software during
configuration.
Reset to 0
14.1.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
Bit
Function
Type
Description
31:24
Secondary
Latency Timer
R/W
Designated in units of PCI bus clocks. Latency timer checks for
master accesses on the secondary bus interfaces that remain
unclaimed by any target.
Reset to 0
14.1.14
I/O BASE REGISTER – OFFSET 1Ch
Bit
Function
Type
Description
3:0
32-bit Indicator
R/O
Read as 01h to indicate 32-bit I/O addressing
7:4
I/O Base Address
[15:12]
R/W
Defines the bottom address of the I/O address range for the bridge
to determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be 0. The upper 16 bits corresponding to address
bits [31:16] are defined in the I/O base address upper 16 bits address
register
Reset to 0
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