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參數(shù)資料
| 型號(hào)： | PI7C8150BNDIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 15/109頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 13 of 109
April 2009 – Revision 1.08
Name
Pin #
Type
Description
P_IRDY_L
82
T10
STS
Primary IRDY (Active LOW). Driven by the initiator
of a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-asserted
state for one cycle.
P_TRDY_L
83
R10
STS
Primary TRDY (Active LOW). Driven by the target
of a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-asserted state
for one cycle.
P_DEVSEL_L
84
P10
STS
Primary Device Select (Active LOW). Asserted by the
target indicating that the device is accepting the
transaction. As a master, PI7C8150B waits for the
assertion of this signal within 5 cycles of P_FRAME_L
assertion; otherwise, terminate with master abort. Before
tri-stated, it is driven to a de-asserted state for one cycle.
P_STOP_L
85
T11
STS
Primary STOP (Active LOW). Asserted by the target
indicating that the target is requesting the initiator to
stop the current transaction. Before tri-stated, it is driven
to a de-asserted state for one cycle.
P_LOCK_L
87
R11
STS
Primary LOCK (Active LOW). Asserted by the
master for multiple transactions to complete.
P_IDSEL
65
P6
I
Primary ID Select. Used as a chip select line for Type
0 configuration access to PI7C8150B configuration
space.
P_PERR_L
88
T12
STS
Primary Parity Error (Active LOW). Asserted when
a data parity error is detected for data received on the
primary interface. Before being tri-stated, it is driven to
a de-asserted state for one cycle.
P_SERR_L
89
P11
OD
Primary System Error (Active LOW). Can be driven
LOW by any device to indicate a system error condition.
PI7C8150B drives this pin on:
Address parity error
Posted write data parity error on target bus
Secondary S_SERR_L asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
This signal requires an external pull-up resistor for
proper operation.
P_REQ_L
47
P2
TS
Primary Request (Active LOW): This is asserted by
PI7C8150B to indicate that it wants to start a transaction
on the primary bus. PI7C8150B de-asserts this pin for at
least 2 PCI clock cycles before asserting it again.
P_GNT_L
46
R1
I
Primary Grant (Active LOW): When asserted,
PI7C8150B can access the primary bus. During idle and
P_GNT_L asserted, PI7C8150B will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
P_RESET_L
43
P1
I
Primary RESET (Active LOW): When P_RESET_L is
active, all PCI signals should be asynchronously tri-
stated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150BNDIE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150DMAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150DND | 制造商:Pericom Semiconductor Corporation 功能描述:BRIDGE 制造商:Pericom Semiconductor Corporation 功能描述:2 PORT PCI BRIDGE - Rail/Tube |
| PI7C8150DNDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150EVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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