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參數(shù)資料
| 型號(hào)： | MT90520AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA456 |
| 封裝： | 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-456 |
| 文件頁(yè)數(shù)： | 86/180頁(yè) |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520AG |
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MT90520
Data Sheet
86
Zarlink Semiconductor Inc.
.
Figure 31 - Overview of CBR Data Reassembly Process (SDT Mode)
4.6.1.6 Clock Recovery Operations
The SDT RX_SAR and the UDT RX_SAR are responsible for generating data required for the performance of clock
recovery operations within the MT90520. In the case of adaptive clock recovery, the active RX_SAR must generate
a digital phaseword for transport to the internal per-port PLL. If SRTS clock recovery is being used, the RX_SAR
extracts 4-bit RTS values from incoming ATM cells and sends them to the corresponding port’s PLL.
Digital Phaseword Generation for Adaptive Clock Recovery
If the user has decided to use adaptive clock recovery to generate the TDM output clock, SToCLK, for a port, the
A
(Adaptive Enable)
bit in the UDT/SDT Reassembly Control Structure for the port must be set. In the UDT case,
there is only one VC per port. However, in the SDT case, only a single VC per port (where the port is identified by
the value in the
VC TDM Port
field of the Reassembly Control Structure) may have its A bit set.
Note:
In addition to
the Reassembly Control Structure, the PLL for the port must also be configured to operate in adaptive mode.
If the A bit is set, the UDT RX_SAR or the SDT RX_SAR is responsible for generating a digital phaseword for the
port’s PLL. These phasewords represent the fill level of the Reassembly Circular Buffer(s) for a port.
In UDT mode, if it is determined that a VC is cut (see Section 4.6.2.1 on page 87), no cells are being received at the
UDT RX_SAR. As a result, there is no frame of reference with which to adjust the output TDM clock rate.
Accordingly, the PLL is placed into holdover mode until cells are once again being received on the VC. At that point,
the output clock rate can be adjusted based on the buffer fill level.
For more information, see Section 4.7.2.6, “Adaptive Clock Recovery Circuit,” on page 102.
TDM
Output
Buffer
DSTo
CSTo
SToCLK
SToMF
TDM Interface
Module (one per
port)
SDT
RX_SAR
UTO_IN_CLK
UTO_IN_ENBATM_CLAVPHY
UTO_IN_CLAVATM_ENBPHY
UTO_IN_SOC
UTO_IN_DATA[15:0]
UTO_IN_PAR
TX
UTOPIA
FIFO
UTOPIA Module
SDT Reassembly
Control Structure
(one per VC in
internal memory)
MT90520
External ZBT SRAM
SDT Reassembly
Circular Buffers (one
per TDM channel)
VC Look-Up
Table
TDM SDT
Reassembly Control
Structure (one per port
in internal memory)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
| MT90820AL | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
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