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參數(shù)資料
| 型號(hào)： | MT90520AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA456 |
| 封裝： | 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-456 |
| 文件頁數(shù)： | 48/180頁 |
| 文件大小： | 1736K |
| 代理商： | MT90520AG |
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MT90520
Data Sheet
48
Zarlink Semiconductor Inc.
Silence Insertion
During an underrun condition bit 10 of TDM Control Register 3, REPLAY_N_SILENCE, is used to indicate whether
old data or a silence byte will be played out onto the TDM bus signal DSTo. This bit is programmable on a per port
basis. When the bit is set to 1 or REPLAY, old data from the reassembly circular buffer will be played out. When the
bit is set to 0 or SILENCE, a programmable silence byte is played out onto the DSTo channel. The silence byte to
be played out is programmed into the Main TDM Control Register 1, bits <15:8>.
When an active channel is mis-reporting an underrun condition the REPLAY_N_SILENCE bit still controls what
data is played out onto the TDM bus. If this bit is set to 1 for REPLAY the correct data will be played out. If the bit is
set to 0 for SILENCE then the silence byte will be played out rather than the correct data. As such, for bit error free
operation, the REPLAY option must be selected for any TDM port where an active channel is mis-reporting an
underrun condition.
Inactive Channels
A recommended solution would be to open a dummy receive VC(s) containing up to 128 inactive channels. This will
increase the prospect that active channels (x) will not mis-report underrun as more (x+4) channels will be active.
The procedure would be as follows
To open a valid receive VC - mask TDM interrupts, close the dummy receive VC(s), open the valid receive
VC, re-open the dummy receive VC(s) (with less channels), unmask the TDM interrupts
To close a valid receive VC - mask TDM interrupts, close the valid receive VC, close the dummy receive
VC(s), re-open the dummy receive VC(s) (with more channels), unmask the TDM interrupts
4.3.2.3 TDM Loopback
There are two loopback modes implemented in the TDM module.
TDM Low-Latency Loopback
The first loopback mode is TDM low-latency loopback, and is enabled by setting the TDM_LOW_LATENCY_LPBK
bit in a port’s TDM Control Register 1. When this bit is set, the TDM data coming in on DSTi is directly output on the
DSTo output line of the same TDM port, with a delay through the device of about two TDM clock cycles.
TDM Circular Buffer Loopback (SDT Mode)
The second loopback is performed at the Circular Buffer level. It can only be used in SDT mode and it is selected by
setting the TDM_CIR_BUF_LPBK bit in a port’s TDM Control Register 1. In this loopback mode, the TDM SDT
reassembly process uses the TDM_SEGMEN_BASE_ADD (in the per-port TDM Control Register 2) as the base
address for the SDT Reassembly Circular Buffers in external memory. This loopback mode can be used to:
loop back an entire stream
loop back certain channels while tristating others
switch the data between various channels (within the same port)
To determine which channels to loop back and their order, the TDM reassembly process reads the TDM SDT
Reassembly Control Structure (refer to Figure 13 on page 46), which should be programmed in the following
manner:
V -
The valid bits should be set for those channels which should be output on DSTo/CSTo. If the valid bit for
a channel is not set, the output channel is tristated.
SU, I, and PU bits -
These bits should be cleared.
Reassembly Circular Buffer Address bits -
bits<9:6> - These bits should be cleared as they are not used in loopback mode.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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