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參數資料
| 型號： | MT90520AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA456 |
| 封裝： | 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-456 |
| 文件頁數： | 79/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520AG |
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MT90520
Data Sheet
79
Zarlink Semiconductor Inc.
module. Underruns occur when the TDM has begun to re-read data from the buffer because it has not been
replaced by new data from the UDT RX_SAR.
If an “okay” condition is detected, the UDT RX_SAR is permitted to write to the UDT Reassembly Circular Buffer at
the location determined by the UDT RX_SAR write pointer from the VC’s UDT Reassembly Control Structure. In the
case of a slip (either an underrun or an overflow), the UDT RX_SAR’s write pointer is adjusted such that the cell is
written to the circular buffer at the location of TDM read pointer + avg_lead. In addition, when slips are detected, the
corresponding MIB statistics fields (
Buffer Underruns
or
Buffer Overflows
) in the active VC’s UDT Reassembly
Control Structure are incremented.
Only in rare instances (e.g., when the TDM output clock, SToCLK, is very different from the TDM input clock,
STiCLK) will slips occur. In such a case, two cells may be written to internal memory before the TDM module can
read a single cell (or, perhaps two cells may be read from memory before another one can be written by the UDT
RX_SAR). Since both the UDT RX_SAR and the TDM module operate with 47-byte blocks of data, it is necessary
to set Maximum Lead to at least 94d (so that the average distance between the read and write pointers is 47d, or
the equivalent of one cell of data). If Maximum Lead is not set to > 94d, even a minor slip (e.g., a cell that arrives
one clock cycle after the TDM starts reading from the buffer) appears as a gross slip (i.e., underrun or overflow).
Because gross slips cause the UDT RX_SAR’s write pointer to be re-aligned, data in the buffers may be
overwritten. As well, if adaptive clock recovery is being used (see Section , “Digital Phaseword Generation for
Adaptive Clock Recovery,” on page 86), repeated gross slips mean that the PLL cannot track the incoming data to
SToCLK, and gross slips will likely continue to occur. The following equation can be used for setting Maximum
Lead:
maxlead = 2*n*CDV+94 where n=256 for E1 and n=193 for DS1, and CDV is in milliseconds.
Overall, the Reassembly Circular Buffers in UDT mode are very large. Therefore, there is ample room to adjust the
value of Maximum Lead and thereby reduce the risk of overflows. It should be stated, however, that the penalty for
a large Maximum Lead value will be a start-up delay: the TDM module will read invalid data until it reaches the
location of “TDM read pointer + avg_lead” at which the UDT RX_SAR started writing to the buffer. Also, there will be
a continuing delay in the reception of data on DSTo because of the distance between the write pointer and the read
pointer (i.e., data written to the buffer by the UDT RX_SAR isn’t immediately read out by the TDM module).
UDT Received Cell Counter
The UDT RX_SAR also provides the user with the number of UDT cells received from the UTOPIA block. This 16-
bit counter value can be viewed in register URCCR at address 2006h. This counter is an overall UDT cell counter: it
is incremented every time a UDT cell is received from the UTOPIA (regardless of whether the cells are discarded by
the UDT RX_SAR). When this counter rolls over, a status bit gets set in the URSR register at address 2004h. This
status bit can be cleared by software. This rollover condition can also generate a service request to the CPU if the
corresponding service enable bit is set.
The user is also provided with a per-VC cell counter. This counter is located in the UDT Reassembly Control
Structure (see Figure 27 on page 68). The operation of this counter is similar to the overall UDT cell counter. When
the per-VC counter rolls over, a status bit gets set in the control structure and can be cleared by the user. The
rollover condition can also generate a request to the CPU if the UDT_REAS_ROLL_SE bit is set in the URSER
register at address 2002h. The CPU can then read the contents of the SERVICE_PORT field of the URSR register
at address 2004h to identify which control structure generated the service request.
SDT Mode of Operation
In “normal” operation (i.e., the SDT RX_SAR’s Fast SN Processing state machine is in “sync”), the SDT RX_SAR is
primarily responsible for transferring TDM and CAS data (if applicable) from SDT cells received at the UTOPIA
interface to multiple SDT Reassembly Circular Buffers in external memory. In addition, SDT pointers must be
analyzed to ensure that the extracted data is being directed to the correct TDM channels.
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相關代理商/技術參數 |
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| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
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