參數資料
型號: MT90520AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數字傳輸電路
英文描述: 8-Port Primary Rate Circuit Emulation AAL1 SAR
中文描述: ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA456
封裝: 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-456
文件頁數: 145/180頁
文件大?。?/td> 1736K
代理商: MT90520AG
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MT90520
Data Sheet
145
Zarlink Semiconductor Inc.
Address: 6206 + p*10 (Hex)
Label: TDM4_Pp (where p represents the port number)
Reset Value: 0040 (Hex)
Label
Bit
Position
Type
Description
Reserved
0
R/O
Always reads ‘0’.
UDT_LOS_SE
1
R/W
UDT Loss of Signal (LOS) Service Enable.
When this bit is set and UDT_LOS_STATUS is asserted, TDM_SRV is set in the Main
Status Register at 0002h.
UDT_TDM_OUT_
BUF_ERROR_SE
2
R/W
UDT TDM Output Buffer Error Service Enable.
When this bit is set and UDT_TDM_OUT_BUF_STATUS is asserted, TDM_SRV is set in
the Main Status Register at 0002h.
SDT_TDM_OUT_
BUF_ERROR_SE
3
R/W
SDT TDM Output Buffer Error Service Enable.
When this bit is set and SDT_TDM_OUT_BUF_STATUS is asserted, TDM_SRV is set in
the Main Status Register at 0002h.
SDT_PERM_
UNDER_SE
4
R/W
SDT Permanent Underrun Service Enable.
When this bit is set and SDT_PERM_UNDER_STATUS is asserted, TDM_SRV is set in the
Main Status Register at 0002h.
SDT_SIMPLE_
UNDER_SE
5
R/W
SDT Simple Underrun Service Enable.
When this bit is set and SDT_SIMPLE_UNDER_STATUS is asserted, TDM_SRV is set in
the Main Status Register at 0002h.
UDT_LOS_
STATUS
6
R/O/L
UDT Loss of Signal (LOS) Status.
This bit is set when a loss of signal is detected on CSTi/LOSi. Writing a ‘0’ to this bit clears it.
This bit cannot be cleared until the TDM Control Register 1 is programmed.
UDT_TDM_OUT_
BUF_STATUS
7
R/O/L
UDT TDM Output Buffer Error Status.
This bit is set when there is an error in the UDT TDM output buffer. Writing a ‘0’ to this bit
clears it.
SDT_TDM_OUT_
BUF_STATUS
8
R/O/L
SDT TDM Output Buffer Error Status.
This bit is set when there is an error in the SDT TDM output buffer. Writing a ‘0’ to this bit
clears it.
SDT_PERM_
UNDER_STATUS
9
R/O/L
SDT Permanent Underrun Status.
This bit is set when a permanent underrun service enable bit is set in the TDM SDT
Reassembly Control Structure for the port and the corresponding permanent underrun
condition occurs. Writing a ‘0’ to this bit clears it.
SDT_SIMPLE_
UNDER_STATUS
10
R/O/L
SDT Simple Underrun Status.
This bit is set when a simple underrun service enable bit is set in the TDM SDT Reassembly
Control Structure for the port and the corresponding simple underrun condition occurs.
Writing a ‘0’ to this bit clears it.
SIMPLE_UNDER
RUN_REPORT
15:11
R/O
SDT Simple Underrun Report.
Indicates the TDM channel on which a “simple underrun” occurred last.
Table 85 - TDM Control Register 4 (one per port)
Address: 6208 + p*10 (Hex)
Label: TDM5_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
PERM_
UNDERRUN_
REPORT
15:0
R/O/L
Permanent Underrun Report. (Applies only to SDT mode.)
This register represents bits<31:16> of the 32-bit permanent underrun report. Bit<31>
corresponds to channel 31, bit<30> corresponds to channel 30, etc.
When an underrun occurs on a certain channel, the corresponding bit is set high; the
microprocessor can clear these bits by writing them to ‘0’.
Table 86 - TDM Control Register 5 (one per port)
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