
MC68F375
CONFIGURABLE TIMER MODULE (CTM9)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
13-54
13.9.2.1 CPCR — CPSM Control Register
13.9.3 Clock Sources for the Counter Submodules
The software chooses one of seven clock sources for each counter. Six of them are
prescaler taps derived from the on-chip oscillator. The highest frequency available to
the counter is the MCU system clock divided by 2. Four of the other five taps are binary
divisible from the system clock cycle — divide by 4, 8, 16, and 32. Another input clock
to the counter is a software defined divide by 64, 128, 256, or 512 from the MCU clock.
There is an alternate prescaler option where the MCU clock is divided by 3, 6, 12, 24,
CPCR — CPSM Control Register
0xYF F208
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
0000
PRUN DIV23
PSEL
1
PSEL
0
RESET:
0
Table 13-21 CPCR Bit Settings
Bit(s)
Name
Description
15:4
—
Reserved
3
PRUN
Prescaler running. The PRUN bit is a read/write control bit that allows the software to switch the
prescaler counter on and off. This bit allows the counters in various CTM submodules to be
synchronized.
0 = Prescaler divider is held in reset and is not running.
1 = Prescaler is running.
2DIV23
Divide by 2 or divide by 3 . The DIV23 bit is a read/write control bit that selects the division ratio
of the first prescaler counter. It may be changed by the software at any time and is cleared on
reset.
0 = First prescaler stage divides by 2.
1 = First prescaler stage divides by 3.
1:0
PSEL[1:0]
Prescaler division ratio select. These control bits select the division ratio of the programmable
Table 13-22 Prescaler Division Ratio Select
Prescaler Control Register Bits
Prescaler Division Ratio
PRUN
DIV23
PSEL1
PSEL0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
0
X
000000
1000248
16
32
64
1001248
16
32
128
1010248
16
32
256
1011248
16
32
512
110036
12
24
48
96
110136
12
24
48
192
111036
12
24
48
384
111136
12
24
48
768
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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