
MC68F375
MASK ROM MODULE
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
12-5
12.4.2 ROM Base Address Register (ROMBAH, ROMBAL)
The default reset ROM base address fields are specified by the user along with the
contents of the array and are programmed on the same mask layer as the contents of
the array.
9:8
ASPC[1:0]
ROM array space. The ASPC[1:0] field is forced to the default reset state by master reset. The
default reset state of the ASPC[1:0] field is specified by the user at mask programming time and
is programmed on the same mask layer as the contents of the array. IFC[2:0] is checked by the
ROM module BIU to determine if a user or supervisor is requesting array access. If a supervisor
program is accessing the array, normal read operation will occur. If a user program is attempting
to access the array, the access will be ignored and the address may be decoded externally.
00 = Unrestricted program and data space IFC[2:0] = x01, x10.
01 = Unrestricted program space only. IFC[2:0] = x10.
10 = Supervisor data and program space only. IFC[2:0] = 101, 110.
11 = Supervisor program space only. IFC[2:0] = 110.
7:6
WAIT[1:0]
Wait states. The WAIT field is used to specify the number of WAIT states inserted by the ROM
BIU during accesses to the ROM module before asserting IDTACKB. A WAIT state has a dura-
tion of one system clock cycle. This affects both control block access and array access. This
feature allows the migration of storage space from a slower emulation or development system
memory to the onboard ROM module without the need for retiming the system. The default reset
state of the WAIT field is specified by the user at mask programming time and is programmed
on the same mask layer as the contents of the array. The WAIT field may be written any time
the LOCK bit is 0.
00 = 3 clocks per transfer.
01 = 4 clocks per transfer
10 = 5 clocks per transfer
11 = 2 clocks per transfer
5:0
—
Reserved
ROMBAH — ROM Base Address High Register
0xYF F824
MSB
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
LSB
16
RESERVED
ROMBAH1
NOTES:
1. Indicates bits protected by LOCK and STOP. The default state of these bits is defined by customer-specified
options.
RESET:
0
U2
2. The default state of these bits is defined by customer specified options.
U2
ROMBAL — ROM Base Address Low Register
0xYF F826
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
ROMBAL1
NOTES:
1. Indicates bits protected by LOCK and STOP. The default state of these bits is defined by customer-specified
options.
RESERVED
RESET:
U2
0
Table 12-2 ROMMCR Bit Settings (Continued)
Bit(s)
Name
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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