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MC68F375
CAN 2.0B CONTROLLER MODULE
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
7-20
Each one of the 16 message buffers can be an interrupt source, if its corresponding
IMASK bit is set. There is no distinction between transmit and receive interrupts for a
particular buffer. Each of the buffers is assigned a bit in the IFLAG register. An IFLAG
bit is set when the corresponding buffer completes a successful transmission/recep-
tion. An IFLAG bit is cleared when the CPU32 reads IFLAG while the associated bit is
set, and then writes it back as zero (and no new event of the same type occurs
between the read and the write actions).
The other three interrupt sources (bus off, error and wake up) act in the same way, and
have flag bits located in the error and status register (ESTAT). The bus off and error
interrupt mask bits (BOFFMSK and ERRMSK) are located in CANCTRL0, and the
wake up interrupt mask bit (WAKEMSK) is located in the module configuration regis-
ter. Table 7-9 shows TouCAN interrupt priorities and their corresponding vector
addresses.
7.8 Programmer’s Model
CAN modules in the MC68F375 address map.
The column labeled “Access” indicates the privilege level at which the CPU must be
operating to access the register. A designation of “S” indicates that supervisor mode
is required. A designation of “S/U” indicates that the register can be programmed for
either supervisor mode access or unrestricted access.
Table 7-9 Interrupt Sources and Vector Addresses
Interrupt Source
Vector Number
Buffer 0
0bXXX00000 (Highest priority)
Buffer 1
0bXXX00001
Buffer 2
0bXXX00010
Buffer 3
0bXXX00011
Buffer 4
0bXXX00100
Buffer 5
0bXXX00101
Buffer 6
0bXXX00110
Buffer 7
0bXXX00111
Buffer 8
0bXXX01000
Buffer 9
0bXXX01001
Buffer 10
0bXXX01010
Buffer 11
0bXXX01011
Buffer 12
0bXXX01100
Buffer 13
0bXXX01101
Buffer 14
0bXXX01110
Buffer 15
0bXXX01111
Bus off
0bXXX10000
Error
0bXXX10001
Wake-up
0bXXX10010 (Lowest priority)
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Freescale Semiconductor, Inc.
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