
MC68F375
CDR MoneT FLASH FOR THE IMB3 (CMFI)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
10-4
MHz to 40.0 MHz.
— Program pulses from 4.0 s to 2.73 ms.
— Erase pulses from 4.096 ms to 2.796 s.
External 4.75 to 5.25 V VPP program and erase power supply.
Array block 0 enable is selected from one of two sources:
— A pin external to the device (EPEB0)
— The inverted state of the CMFI PROTECT bit.
Data word length of 16 bits.
Supports IMB3 burst read accesses.
— Contains two separate non-sequential burst buffers.
— Burst buffer size of 32 bytes.
— Burst terminated at end of buffer or by IMB3.
Software mapping to establish array base address.
Emulation support
— Support for integration modules with external emulation through a special chip
select.
— Supports internal emulation through memory overlay option.
Low power disable via the integration module.
Wait states for integration from slower external memory.
10.1.3 Glossary of terms used in the CMFI EEPROM Specification
Array block — CMFI array subdivision: a 32-Kbyte contiguous block of information.
Each array block may be erased independently.
BIU — Bus interface unit controls access and operation of the CMFI array through a
standard IMB3 interface.
Burst read — Array read operation that requires 2 clocks for the first data access and
1 clock for the following data accesses.
CMFI — The CDR MoneT FLASH EEPROM for the IMB3.
Erase interlock write — A write to any CMFI array address after initializing the erase
sequence.
Erase margin read — Special burst buffer updates of the CMFI array where the CMFI
EEPROM hardware adjusts the reference of the sense amplifier to check for correct
erase operation. All CMFI array burst buffer updates between the erase interlock write
and clearing the SES bit are erase margin reads.
IM — Integration module.
IMB3 — A motherboard-on-a-chip for embedded controller designs.
Notable features of the bus architecture include: burst data transfers, multiple bus
masters, exception processing support, address space partitioning, multiple interrupt
levels, vectored interrupts, and extendable bus cycles via wait state insertion.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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