![](http://datasheet.mmic.net.cn/Freescale-Semiconductor/MC68F375MZP33R2_datasheet_98733/MC68F375MZP33R2_232.png)
MC68F375
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
5-56
5.13.3 Pin Connection and Performance Considerations
The performance of an ANXx pin is almost the same as that of an ANx input to the
QADC64. There are two differences: there is an increased resistance because of the
additional multiplexer switch in series, and there is no buffering between channels
within the groups of 8. If the increased resistance becomes a problem it can be com-
pensated for by increasing the input sample time (IST[7:6] in the Conversion
Command Word Table of the QADC64). The lack of buffering between channels
causes additional dynamic charging current to flow into the analog pins during succes-
sive conversions of different voltages. A schematic of one group of eight inputs which
illustrates the cause of this charging current is shown in figure Figure 5-14.
If alternating between 2 AMUX channels within the group of eight, one at Vrh and the
other at Vrl, the equivalent capacitance CEQ must be charged/discharged between Vrh
and Vrl. This generates an average current which flows across the sum of the filter,
source, and mux resistances. The error due to the charging current is expressed by
the following equation:
ERROR = IAVG * REQ = V * sample_rate * CEQ * REQ
Where: CEQ = CMUXOUT + CP
REQ = RSOURCE + RFILTER + RMUXOUT
V = Vrh - Vrl
For an error equal to 1/2 LSB, the following equation must be met:
CEQ * REQ < 1/(2048*sample_rate)
As an example, if CEQ = 2.0 pF and REQ = 50K, the maximum sample_rate is 4.9 KHz.
This charging current is also present on normal QADC64 channels, but to a lesser
extent because CMUXOUT and RMUXOUT are both zero.
For a discussion of other pin connection and performance considerations, please refer
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.