MC68F375
TIME PROCESSOR UNIT 3
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
8-13
8.4.4 Development Support Status Register
4BC
Channel breakpoint enable
0 = Breakpoint not enabled
1 = Break if CHAN register equals channel breakpoint register at beginning of state or when
CHAN is changed through microcode
3BH
Host service breakpoint enable
0 = Breakpoint not enabled
1 = Break if host service latch is asserted at beginning of state
2BL
Link service breakpoint enable
0 = Breakpoint not enabled
1 = Break if link service latch is asserted at beginning of state
1BM
MRL breakpoint enable
0 = Breakpoint not enabled
1 = Break if MRL is asserted at beginning of state
0BT
TDL breakpoint enable
0 = Breakpoint not enabled
1 = Break if TDL is asserted at beginning of state
DSSR — Development Support Status Register
0xYF FE06
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
RESERVED
BKPT
PCBK CHBK SRBK
TPUF
RESERVED
RESET:
0
Table 8-8 DSSR Bit Settings
Bit(s)
Name
Description
15:8
—
Reserved
7
BKPT
Breakpoint asserted flag. If an internal breakpoint caused the TPU3 to enter the halted state, the
TPU3 asserts the
BKPT signal on the IMB and sets the BKPT flag. BKPT remains set until the
TPU3 recognizes a breakpoint acknowledge cycle, or until the IMB FREEZE signal is asserted.
6PCBK
PC breakpoint flag. PCBK is asserted if a breakpoint occurs because of a PC (microprogram
counter) register match with the
PC breakpoint register. PCBK is negated when the BKPT flag
is cleared.
5CHBK
Channel register breakpoint flag. CHBK is asserted if a breakpoint occurs because of a CHAN
register match with the CHAN register breakpoint register. CHBK is negated when the BKPT flag
is cleared.
4SRBK
Service request breakpoint flag. SRBK is asserted if a breakpoint occurs because of any of the
service request latches being asserted along with their corresponding enable flag in the devel-
opment support control register. SRBK is negated when the BKPT flag is cleared.
3TPUF
TPU3 FREEZE flag. TPUF is set whenever the TPU3 is in a halted state as a result of FREEZE
being asserted. This flag is automatically negated when the TPU3 exits the halted state because
of FREEZE being negated.
2:0
—
Reserved
Table 8-7 DSCR Bit Settings (Continued)
Bit(s)
Name
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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