
MC68F375
DUAL-PORT TPU RAM (DPTRAM)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
9-5
9.4.4 MISR High (MISRH) and MISR Low (MISRL)
The MISRH and MISRL together contain the 32-bit RAM signature calculated by the
MISC. These registers are read-only and should be read by the host when the MISF
bit in the MCR is set. Note that the naming of the D[31:0] bits represents little-endian
bit encoding.
Exiting TPU3 emulation mode results in the reset of both MISRH and MISRL
DPTBAR — RAM Array Base Address Register
0xYF F884
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
Reserved
RAMDS
RESET:
0
1
Table 9-3 DPTBAR Bit Settings
Bit(s)
Name
Description
15:5
A[8:18]
RAM array base address. These bits specify the 11 high-order bits (address lines ADDR[8:18]
in little-endian notation) of the 24-bit base address of the RAM array. This allows the array to be
placed on a 8-Kbyte boundary anywhere in the memory map. It is the users responsibility not to
overlap the RAM array memory map with other modules on the chip.
4:1
—
Reserved. (Bits 11:12 represent A[12:11] in DPTRAM implementation that require them.)
0RAMDS
RAM disabled. RAMDS is a read-only status bit. The RAM array is disabled after a master reset
since the RAMBAR register may be incorrect. When the array is disabled, it will not respond to
any addresses on the IMB3. Access to the RAM control register block is not affected when the
array is disabled.
RAMDS is cleared by the DPTRAM module when a base address is written to the array address
field of RAMBAR.
RAMDS = 0: RAM enabled
RAMDS = 1: RAM disabled
MISRH — Multiple Input Signature Register High
0xYF F886
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
RESET:
0
MISRL — Multiple Input Signature Register Low
0xYF F888
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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