參數(shù)資料
型號： LU3X32FT
廠商： Lineage Power
英文描述： Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
中文描述： 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網(wǎng)收發(fā)器）
文件頁數(shù)： 8/54頁
文件大?。?/td> 626K
代理商： LU3X32FT
LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
8
Lucent Technologies Inc.
Table 6. 100 Base-X PCS Configuration
Note: Many of these signals are dual-function pins. During reset, these pins may be pulled up or down (as shown in Figure 5) to configure
various options. The secondary function is shown in smaller
print and described in Table 9.
Table 7. Autonegotiation Configuration
Pin No.
111, 56
Pin Name
BPSCR
/LEDTX/
ACTLED
[1:0]
I/O
I/O
Pin Description
Bypass Scrambler Mode (Ports 1, 0)
. A high value on
this pin during powerup or reset will bypass the scram-
ble/descramble operations in the 100Base-X data path.
This pin has an internal 40 k
pull-down. In fiber mode,
this pin should be pulled high. See Table 9 for LEDTX
and ACTLED description.
114, 53
BPALIGN
/LEDLNK
[1:0]
I/O
Bypass Alignment Mode (Ports 1, 0)
. A high value on
this pin during powerup or reset will bypass the align-
ment feature of the PHY. This bypass mode provides a
symbol interface. This pin has an internal 40 k
pull-
down. See Table 9 for LEDLNK description.
112, 55
BP4B5B/
LEDCOL
[1:0]
I/O
Bypass 4B5B Mode.
A high value on this pin during
powerup or reset will bypass the 4B/5B encoder of the
PHY. This pin has an internal 40 k
pull-down. See
Table 9 for LEDCOL description.
Pin No.
122, 45
Pin Name
AUTONEN[1:0]
I/O
I
Pin Description
Autonegotiation Enable (Ports 1, 0)
. A high value on
these pins during powerup or reset will enable autone-
gotiation, a low value will disable it.
100 Full-Duplex Enable (Ports 1, 0)
. Logic level of this
pin is detected at powerup or reset to determine whether
100 Mbits/s full-duplex mode is available. The 100
Mbits/s full-duplex mode is available only if NDPRTR pin
is low during reset indicating node operation. When
autonegotiation is enabled, this input sets the ability
register bit in advertisement register 4. When autonego-
tiation is not enabled, this input will select the mode of
operation. See Table 8 for CIMEN description.
10 Full-Duplex Enable (Ports 1, 0)
. Logic level of this
pin is detected at powerup or reset to determine whether
10 Mbits/s full-duplex mode is available. The
10 Mbits/s full-duplex mode is available only if NDPRTR
pin is low during reset indicating node operation. When
autonegotiation is enabled, this input sets the ability
register bit in advertisement register 4. When autonego-
tiation is not enabled, this input will select the mode of
operation. This pin has an internal 40 k
pull-up resistor.
See Table 9 for LEDSP description.
125, 42
100FDEN
/CIMEN
[1:0]
I
85, 82
10FDEN
/LEDSP
[1:0]
I/O
Pin Descriptions
(continued)
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