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參數(shù)資料
| 型號： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 19/54頁 |
| 文件大?。?/td> | 626K |
| 代理商： | LU3X32FT |
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Lucent Technologies Inc.
19
Preliminary Data Sheet
July 2000
LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Functional Description
(continued)
NRZI/NRZ & Serial/Parallel Conversion
. The recovered data is converted from NRZI to NRZ format. The data is
not necessarily aligned to 4B/5B code-group’s boundary.
Data Descrambling
. The descrambler acquires synchronization with the data stream by recognizing IDLE bursts
of 40 or more bits and locking its deciphering linear feedback shift register (LFSR) to the state of the scrambling
LFSR. Upon achieving synchronization, the incoming data is XORed by the deciphering LFSR and descrambled.
In order to maintain synchronization, the descrambler continuously monitors the validity of the unscrambled data
that it generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the synchroni-
zation status. Upon synchronization of the descrambler, the hold timer starts a 722
μ
s countdown. Upon detection
of sufficient IDLE symbols within the 722
μ
s period, the hold timer will reset and begin a new countdown. This mon-
itoring operation will continue indefinitely given a properly operating network connection with good signal integrity.
If the link state monitor does not recognize sufficient unscrambled IDLE symbols within the 722
μ
s period, the
descrambler will be forced out of the current state of synchronization and reset in order to reacquire synchroniza-
tion. Register 18h, bit 3, can be used to extend the timer to 2 ms.
Symbol Alignment
. The symbol alignment circuit in the LU3X32FT determines code word alignment by recogniz-
ing the /J/K delimiter pair. This circuit operates on unaligned data from the descrambler. Once the /J/K symbol pair
(11000 10001) is detected, subsequent data is aligned on a fixed boundary.
Symbol Decoding
. The symbol decoder functions as a look up table that translates incoming 5B symbols into 4B
nibbles. The symbol decoder first detects the /J/K symbol pair preceded by IDLE symbols and replaces the symbol
with MAC preamble. All subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of
the entire packet. This conversion ceases upon the detection of the /T/R symbol pair denoting the end of stream
delimiter (ESD). The translated data is presented on the RXD[3:0] signal lines with RXD[0] represents the least-
significant-bit of the translated nibble.
Valid Data Signal
. The receive data valid signal (RXDV) indicates that recovered and decoded nibbles are being
presented on the RXD[3:0] outputs synchronous to RXCLK. RXDV is asserted when the first nibble of translated /
J/K is ready for transfer over the media independent interface (MII). It remains active until either the /T/R delimiter
is recognized, link test indicates failure, or no signal is detected. On any of these conditions, RXDV is deasserted.
Receiver Errors
. The RXER signals are used to communicate receiver error conditions. While the receiver is in a
state of holding RXDV asserted, the RXER will be asserted for each code word that does not map to a valid code-
group.
100Base-X Link Monitor
The 100Base-X link monitor function allows the receivers to ensure that reliable data is being received. Without
reliable data reception, the link monitor will halt both transmit and receive operations until such time that a valid link
is detected.
The LU3X32FT performs the link integrity test as outlined in IEEE100Base-X (Clause 24) Link Monitor state dia-
gram. The link status is multiplexed with 10 Mbits/s link status to form the reportable link status bit in serial man-
agement register 1, and driven to the LEDLNK pin.
When persistent signal energy is detected on the network, the logic moves into a link-ready state after approxi-
mately 500
μ
s and waits for an enable from the autonegotiation module. When received, the link-up state is
entered, and the transmit and receive logic blocks become active. Should autonegotiation be disabled, the link
integrity logic moves immediately to the link-up state after entering the link-ready state.
相關(guān)PDF資料 |
PDF描述 |
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| LU3X34FT | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| LU3X51FT-J80 | Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網(wǎng)收發(fā)器) |
| LU3X54FTL | Quad-FET for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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