- 您現在的位置：買賣IC網 > PDF目錄384634 > LU3X32FT (Lineage Power) Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網收發(fā)器) PDF資料下載
參數資料
| 型號： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網收發(fā)器） |
| 文件頁數： | 14/54頁 |
| 文件大?。?/td> | 626K |
| 代理商： | LU3X32FT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
14
Lucent Technologies Inc.
Functional Description
(continued)
Management Register Access
. The SMI consists of two pins, management data clock (MDC) and management
data input/output (MDIO). The LU3X32FT is designed to support an MDC frequency ranging up to the IEEEspeci-
fication of 2.5 MHz. Each MDIO line is bidirectional and may be shared by up to 32 devices (16 LU3X32FT
devices).
The MDIO pin requires a pull-up resistor which, during IDLE and turnaround periods, will pull MDIO to a logic one
state. Each MII management data frame is 64 bits long. The first 32 bits are preamble consisting of 32 contiguous
logic one bits on MDIO and 32 corresponding cycles on MDC. Following preamble is the start-of-frame field indi-
cated by a <01> pattern. The next field signals the operation code (OP): <10> indicates READ from MII manage-
ment register operation, and <01> indicates WRITE to MII management register operation. The next two fields are
PHY device address and MII management register address. Both of them are 5-bits wide, and the most-significant
bit is transferred first.
During READ operation, a 2-bit turnaround (TA) time spacing between register address field and data field is pro-
vided for the MDIO to avoid contention. Following the turnaround time, a 16-bit data stream is read from or written
into the MII management registers of the LU3X32FT.
The LU3X32FT supports a preamble suppression mode as indicated by a 1 in bit 6 of the basic mode status regis-
ter (BMSR, address 01h.) If the station management entity (i.e., MAC or other management controller) determines
that all PHYs in the system support preamble suppression by reading a 1 in this bit, then the station management
entity need not generate preamble for each management transaction. The LU3X32FT requires a single initialization
sequence of 32 bits of preamble following powerup/hardware reset. This requirement is generally met by the man-
datory pull-up resistor on MDIO or the management access made to determine whether preamble suppression is
supported. While the LU3X32FT will respond to management accesses without preamble, a minimum of one idle
bit between management transactions is required as specified in IEEE802.3U.
The PHY device addresses for the LU3X32FT are stored in the PHY address registers (register address 19h). It is
initialized by the four I/O pins designated as PHY[4:1] during powerup or hardware reset. PHY[0] is forced to 0 for
port 0 and 1 for port 1. The entire PHY address can be changed by writing into PHY address register, address 19h.
MDIO Interrupt
. The LU3X32FT implements interrupt capability that can be used to notify the management station
of certain events. It generates an active-low interrupt pulse on the MDIOINT output pin whenever one of the inter-
rupt status registers (register address 1Eh) becomes set while its corresponding interrupt mask register (register
address 1Dh) is unmasked. Reading the interrupt status register (register 1Eh) shows the source of the interrupts,
and clears all bits of the interrupt status register.
In addition to the MDIOINT pins, the LU3X32FT can also support the interrupt scheme used by the
TIThunderLAN
* MAC. This option can be enabled by setting bit 11 of register 17h. Whenever this bit is set, the
interrupt is signaled through both the MDIOINT pin and embedded in the MDIO signal.
* TI is a registered trademark and ThunderLANis a trademark of Texas Instruments, Inc.
相關PDF資料 |
PDF描述 |
|---|---|
| LU3X34FT | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網收發(fā)器) |
| LU3X51FT-J80 | Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網收發(fā)器) |
| LU3X54FTL | Quad-FET for 10Base-T/100Base-TX/FX(應用于10基數-T和100基數-TX/FX的四快速以太網收發(fā)器) |
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網收發(fā)器) |
| LUC4AB01 | ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM)) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
發(fā)布緊急采購，3分鐘左右您將得到回復。