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參數(shù)資料
| 型號： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 12/54頁 |
| 文件大?。?/td> | 626K |
| 代理商： | LU3X32FT |
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LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
12
Lucent Technologies Inc.
Functional Description
The LU3X32FT integrates a 100Base-X physical sublayer (PHY), a 100Base-TX physical medium dependent
(PMD) transceiver and a complete 10Base-T module into a single chip for both 10 Mbits/s and 100 Mbits/s Ethernet
operation for two-ports. It also supports 100Base-FX operation through external fiber-optic transceivers. This
device provides two IEEE802.3U compliant media independent interfaces (MII) to communicate between the phys-
ical signaling and the medium access control (MAC) layers for both 100Base-X and 10Base-T operations. The
device is capable of operating in either full-duplex mode or half-duplex mode in either 10 Mbits/s or 100 Mbits/s
operation independently per port. Operational modes can be selected by hardware configuration pins or software
settings of management registers, or they can be determined by the on-chip autonegotiation logic.
The 10Base-T section of each port consists of the 10 Mbits/s transceiver modules with filters and Manchester
ENDEC modules.
The 100Base-X section of the each port implements the following functional blocks:
I
100Base-X physical coding sublayer (PCS)
I
100Base-X physical medium attachment (PMA)
I
Twisted-pair transceiver (PMD)
The 100Base-X and 10Base-T sections of each port share the following functional blocks:
I
Clock synthesizer module (CSM)
I
MII registers
I
IEEE 802.3U autonegotiation
Each of these functional blocks is described below.
Media Independent Interface (MII)
The LU3X32FT implements an IEEE 802.3U Clause 22 compliant MII interface as described below.
Interface Signals
Transmit Data Interface
. Each MII transmit data interface comprises seven signals: TXD[3:0] are the nibble size
data path, TXEN signals the presence of data on TXD, TXER indicates substitution of data with the HALT symbol,
and TXCLK carries the transmit clock that synchronizes all the transmit signals. In node mode, TXCLK is supplied
by the on-chip clock synthesizer; in 100 Mbits/s repeater mode, transmit signals are synchronized to the clock on
XIN pin; in 10 Mbits/s repeater mode operation, an external clock must be connected to the RPTR10CLK pin to
synchronize the data transfer.
Receive Data Interface
. Each MII receive data interface also comprises seven signals: RXD[3:0] are the nibble
size data path, RXDV signals the presence of data on RXD, RXER indicates the validity of data, and RXCLK carries
the receive clock. Depending upon the operation mode, RXCLK signal is generated by the clock recovery module
of either the 100Base-X or 10Base-T receiver.
Status Interface
. Two status signals, COL and CRS, are generated in the LU3X32FT to indicate collision status
and carrier sense status to the MAC for each port. COL is asserted asynchronously whenever that port is transmit-
ting and receiving at the same time in a half-duplex operation mode. In full-duplex mode, COL is inactive. For
repeater mode operation, the COL signal line indicates false carrier sense condition. CRS is asserted asynchro-
nously whenever there is activity on either the transmitter or the receiver. In repeater or full-duplex mode, CRS is
asserted only when there is activity on the receiver.
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相關(guān)代理商/技術(shù)參數(shù) |
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| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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