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參數(shù)資料
| 型號(hào)： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 30/54頁 |
| 文件大?。?/td> | 626K |
| 代理商： | LU3X32FT |
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LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
30
Lucent Technologies Inc.
Register Description
(continued)
Table 16. Status Register Bit Definitions (Per Port) [Register 1h]
Bit(s)
15
Name
Description
R/W
RO
Default
0h
100Base-T4
1—Capable of 100Base-T4.
0—Not capable of 100Base-T4.
This bit is hardwired to 0, indicating that the
LU3X32FT does not support 100Base-T4.
1—Capable of 100Base-X full-duplex mode.
0—Not capable of 100Base-X full-duplex mode.
This bit is hardwired to 0, indicating that the
LU3X32FT does not support 100Base-X full-
duplex mode.
1—Capable of 100Base-X half-duplex mode.
0—Not capable of 100Base-X half-duplex mode.
This bit is hardwired to 1, indicating that the
LU3X32FT supports 100Base-X half-duplex
mode.
1—Capable of 10 Mbits/s full-duplex mode.
0—Not capable of 10 Mbits/s full-duplex mode.
This bit is hardwired to 0, indicating that the
LU3X32FT does not support 10Base-T full-
duplex mode.
1—Capable of 10 Mbits/s half-duplex mode.
0—Not capable of 10 Mbits/s half-duplex mode.
This bit is hardwired to 1, indicating that the
LU3X32FT supports 10Base-T half-duplex
mode.
1—Capable of 100Base-T2.
0—Not capable of 100Base-T2.
This bit is hardwired to 0, indicating that the
LU3X32FT does not support 100Base-T2.
Ignore when read.
14
100Base-X Full Duplex
RO
1h
13
100Base-X Half Duplex
RO
1h
12
10 Mbits/s Full Duplex
RO
1h
11
10 Mbits/s Half Duplex
RO
1h
10
100Base-T2
RO
0h
9:7
6
Reserved
RO
RO
0h
1h
MF Preamble Suppression 1—Accepts management frames with preamble
suppressed.
0—Will not accept management frames with pre-
amble suppressed.
This bit is hardwired to 1, indicating that the
LU3X32FT accepts management frame without
preamble. A minimum of 32 preamble bits are
required following power-on or hardware reset.
One idle bit is required between any two man-
agement transactions as per IEEE802.3u speci-
fication.
Autonegotiation Complete
1—Autonegotiation process completed.
0—Autonegotiation process not completed.
If autonegotiation is enabled, this bit indicates
whether the autonegotiation process has been
completed.
5
RO
0h
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X34FT | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| LU3X51FT-J80 | Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網(wǎng)收發(fā)器) |
| LU3X54FTL | Quad-FET for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器) |
| LUC4AB01 | ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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