參數(shù)資料
型號(hào)： LU3X32FT
廠商： Lineage Power
英文描述： Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
中文描述： 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬(wàn)位和100米位以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 13/54頁(yè)
文件大?。?/td> 626K
代理商： LU3X32FT
Lucent Technologies Inc.
13
Preliminary Data Sheet
July 2000
LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Functional Description
(continued)
Operation Modes
Each port of the LU3X32FT supports three operation modes and an isolate mode as described below.
100 Mbits/s Mode
. For 100 Mbits/s operation, the MII operates in nibble mode with a clock rate of 25 MHz. In nor-
mal operation, the MII data at RXD[3:0] and TXD[3:0] are 4-bit wide. In bypass mode (either BYP_4B5B or
BYP_ALIGN option selected), the MII data takes the form of 5-bit code-groups. The least significant 4 bits appear
on TXD[3:0] and RXD[3:0] as usual, and the most significant bits (TXD[4] and RXD[4]) appear on the TXER and
RXER pins, respectively.
10 Mbits/s Nibble Mode
. For 10 Mbits/s nibble mode operation, the TXCLK and RXCLK operate at 2.5 MHz. The
data paths are 4 bits wide using TXD[3:0] and RXD[3:0] signal lines. This mode is not supported for repeaters.
10 Mbits/s Serial Mode
. The LU3X32FT implements a serial mode for 10Base-T repeater applications. This mode
is selected by strapping the NDRPTR pin (57, 110) and SRL10 pin (pins 1, 38) to logic high level and hold FOSEL
pin (pins 116, 51) at logic low level during powerup or reset. When operating in this mode, the LU3X32FT accepts
NRZ serial data on the TXD[0] input and provides NRZ serial data output on RXD[0] with a clock rate of 10 MHz.
The unused MII signals TXD[3:1], RXD[3:1], and RXDV are ignored during serial mode. The PCS control signals
CRS and COL continue to function normally.
MII Isolate Mode
. The LU3X32FT implements an MII isolate mode that is controlled by bit 10 of the control register
(register address 0h). The LU3X32FT will set this bit to one if the PHY address is set to 00000 upon powerup/hard-
ware reset. Otherwise, the LU3X32FT will initialize this bit to 0. Setting the bit to a 1 will also put the PHY in MII iso-
late mode. Note that port 1 cannot powerup/reset into isolate mode, since its PHY[0] is forced to 1; however, it can
be programmed into isolate mode by setting bit 10 of the control register (register 0h).
The isolate mode can also be activated by setting the PHY address (bits 4 through 0 of register 19h) to 0 through
the serial management interface, although the content of the isolate register is not affected by the modification of
PHY address.
In isolate mode, the LU3X32FT does not respond to packet data present at TXD[3:0], TXEN, and TXER inputs and
presents a high impedance on the TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL, and CRS outputs. The
LU3X32FT will continue to respond to all management transactions.
Serial Management Interface
Each port of the LU3X32FT supports SMI. The serial management interface (SMI) is used to both obtain status
from and to configure each PHY. This mechanism corresponds to the MII spec for 100Base-X (Clause 22) and sup-
ports registers 0 through 6. Additional vendor-specific registers are implemented within the range of 16 to 31. All
the registers are described in the register section.
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