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參數(shù)資料
| 型號： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 23/54頁 |
| 文件大?。?/td> | 626K |
| 代理商： | LU3X32FT |
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Lucent Technologies Inc.
23
Preliminary Data Sheet
July 2000
LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Functional Description
(continued)
SQE Test Function
. Approximately 1
μ
s after the transmission of each packet, a signal quality error (SQE) signal
of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a
pulse on the COL signal of the MII. This function can be enabled by setting bit 12 of register 1Ah. The SQE test
function is disabled in full-duplex mode.
Jabber Function
. The jabber function monitors the LU3X32FTs output and disables the transmitter if it attempts to
transmit a longer than legal-sized packet. If TXEN is high for greater than 24 ms, the 10Base-T transmitter will be
disabled and COL will go active-high.
Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is
asserted. This signal has to be deasserted for approximately 256 ms (the unjab time) before the jabber function
reenables the transmit outputs and de-asserts COL signal.
The jabber function can be disabled by setting bit 10 of register 1Ah.
Link Test Function
. A link pulse is used to check the integrity of the connection with the remote end. If valid link
pulses are not received, the link detector disables the 10Base-T twisted-pair transmitter, receiver, and collision
detection functions.
The link pulse generator produces pulses as defined in the IEEE802.3 10Base-T standard. Each link pulse is
nominally 100 ns in duration and is transmitted every 16 ms, in the absence of transmit data.
Automatic Link Polarity Detection
. The LU3X32FT's 10Base-T transceiver modules incorporate an automatic
link polarity detection circuit. The inverted polarity is determined when seven consecutive link pulses of inverted
polarity or three consecutive receive packets are received with inverted end-of-packet pulses. If the input polarity is
reversed, the error condition will be automatically corrected and reported in bit 15 of register 1Ch.
The automatic link polarity detection function can be disabled by setting bit 3 of register 1Ah.
Clock Synthesizer
The LU3X32FT implements a clock synthesizer that generates all the reference clocks needed from a single exter-
nal frequency source. The clock source must be a TTL level signal at 25 MHz ± 50 ppm, as shown in Figure 15.
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| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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