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參數(shù)資料
| 型號(hào)： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬(wàn)位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁(yè)數(shù)： | 29/54頁(yè) |
| 文件大小： | 626K |
| 代理商： | LU3X32FT |
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Lucent Technologies Inc.
29
Preliminary Data Sheet
July 2000
LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Register Description
(continued)
Table 15
.
Control Register (Per Port) [Register 0h]
(continued)
Bit(s)
10
Name
Isolate
Description
R/W
R/W
Default
Pins
1—Isolate PHY from MII.
0—Normal operation.
Setting this control bit isolates the part
from the MII, with the exception of the
serial management interface. When this
bit is asserted, the LU3X32FT does not
respond to TXD[3:0], TXEN, and TXER
inputs, and it presents a high impedance
on its TXCLK, RXCLK, RXDV, RXER,
RXD[3:0], COL, and CRS outputs. This bit
is initialized to 0 unless the configuration
pins for the PHY address are set to
00000h during powerup or reset.
1—Restart autonegotiation process.
0—Normal operation.
Setting this bit while autonegotiation is
enabled forces a new autonegotiation pro-
cess to start. This bit is self-clearing and
returns to 0 after the autonegotiation pro-
cess has commenced.
1—Full-duplex mode.
0—Half-duplex mode.
If autonegotiation is disabled, this bit
determines the duplex mode for the link.
At powerup or reset, this bit is set to 0 if
the NDRPTR bit indicates REPEATER
operation. Otherwise, this bit is set to 1 if
AUTONEN pin detects a logic 0 and either
100FDEN or 10FDEN pin detects a logic
1.
1—Enable COL signal test.
0—Disable COL signal test.
When set, this bit will cause the COL sig-
nal of MII interface to be asserted in
response to the assertion of TXEN.
Not used.
9
Restart Autonegotiation
R/W, SC
0h
8
Duplex Mode
R/W
Pin
7
Collision Test (only applica-
ble while in PHY loopback
mode)
R/W
0h
6:0
Reserved
RO
0h
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