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參數(shù)資料
| 型號： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 28/54頁 |
| 文件大小： | 626K |
| 代理商： | LU3X32FT |
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LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
28
Lucent Technologies Inc.
Register Description
(continued)
Table 15. Control Register (Per Port) [Register 0h]
Bit(s)
15
Name
Reset
Description
R/W
R/W
SC
Default
0h
1—PHY reset.
0—Normal operation.
Setting this bit initiates the software reset
function that resets the entire LU3X32FT
device, except for the phase-locked loop
circuit. It will relatch in all hardware config-
uration pin values and set all registers to
their default values. The software reset
process takes 25
μ
s to complete. This bit,
which is self-clearing, returns a value of 1
until the reset process is complete.
1—Enable loopback mode.
0—Disable loopback mode.
This bit controls the PHY loopback opera-
tion that isolates the network transmitter
outputs (TPTX± and FOTX±) and routes
the MII transmit data to the MII receive
data path. This function should only be
used when autonegotiation is disabled
(bit 12 = 0). The specific PHY (10Base-T
or 100Base-X) used for this operation is
determined by bits 12 and 13 of this regis-
ter.
1—100 Mbits/s.
0—10 Mbits/s.
Link speed is selected by this bit or by
autonegotiation if bit 12 of this register is
set (in which case, the value of this bit is
ignored). At powerup or reset, this bit will
be set unless AUTONEN, 100FDEN, and
100HDEN pin are all in logic low state.
1—Enable autonegotiation process.
0—Disable autonegotiation process.
This bit determines whether the link speed
should be set up by the autonegotiation
process. It is set at powerup or reset if the
AUTONEN pin detects a logic 1 input
level.
1—Powerdown.
0—Normal operation.
Setting this bit puts the LU3X32FT into
powerdown mode. During the powerdown
mode, TX± and all LED outputs are tri-
stated, FOTX± output are turned off, and
the MII interface is isolated. RSTZ is used
to clear register.
14
Loopback
R/W
0h
13
Speed Selection
R/W
Pin
12
Autonegotiation Enable
R/W
Pin
11
Powerdown
R/W
0h
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