- 您現(xiàn)在的位置：買賣IC網 > PDF目錄384634 > LU3X32FT (Lineage Power) Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網收發(fā)器） |
| 文件頁數(shù)： | 22/54頁 |
| 文件大小： | 626K |
| 代理商： | LU3X32FT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
22
Lucent Technologies Inc.
Functional Description
(continued)
Operation Modes
The LU3X32FT 10Base-T modules are capable of operating in either half-duplex mode or full-duplex mode. In half-
duplex mode, the LU3X32FT functions as an IEEE802.3 compliant transceiver with fully integrated filtering. The
COL pin signals squelch jabber, and the CRS is asserted during transmit and receive. In full-duplex mode, the
LU3X32FT can simultaneously transmit and receive data.
Manchester Encoder/Decoder
. Data encoding and transmission begins when the transmit enable input (TXEN)
goes high and continues as long as the transceiver is in good link state. Transmission ends when the transmit
enable input goes low. The last transition occurs at the center of the bit cell if the last bit is a 1, or at the boundary
of the bit cell if the last bit is 0.
Decoding is accomplished by a differential input receiver circuit and a phase-locked loop that separates the
Manchester-encoded data stream into clock signals and NRZ data. The decoder detects the end of a frame when
no more mid-bit transitions are detected. Within one and a half bit times after the last bit, carrier sense is de-
asserted.
Transmit Driver and Receiver
. LU3X32FT integrates all the required signal conditioning functions in its 10Base-T
blocks such that external filters are not required. Only an isolation transformer and impedance matching resistors
are needed for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all the har-
monics in the transmit signal are attenuated properly.
Smart Squelch
. The smart squelch circuit is responsible for determining when valid data is present on the differen-
tial receive. The LU3X32FT implements an intelligent receive squelch on the TPRX± differential inputs to ensure
that impulse noise on the receive inputs will not be mistaken for a valid signal. The squelch circuitry employs a
combination of amplitude and timing measurements (as specified in the IEEE802.3 10Base-T standard) to deter-
mine the validity of data on the twisted-pair inputs.
The signal at the start of the packet is checked by the analog squelch circuit, and any pulses not exceeding the
squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is
overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally, the signal must
exceed the original squelch level within a further 150 ns to ensure that the input waveform will not be rejected.
Only after all of these conditions have been satisfied will a control signal be generated to indicate to the remainder
of the circuitry that valid data is present.
Valid data is considered to be present until the squelch level has not been generated for a time longer than
200 ns, indicating end-of-packet. Once good data has been detected, the squelch levels are reduced to minimize
the effect of noise causing premature end-of-packet detection. The receive squelch threshold level can be lowered
for use in longer cable applications. This is achieved by setting bit 11 or register address 1Ah.
Carrier Sense
. Carrier sense (CRS) may be asserted due to receive activity once valid data is detected via the
smart squelch function.
For 10 Mbits/s half-duplex operation, CRS is asserted during either packet transmission or reception.
For 10 Mbits/s full-duplex operation, the CRS is asserted only due to receive activity. In repeater mode, CRS is only
asserted due to receive activity. CRS is deasserted following an end of packet.
Collision Detection
. For half-duplex operation, a 10Base-T collision is detected when the receive and transmit
channels are active simultaneously. Collisions are reported by the COL signal on the MII. If the ENDEC is transmit-
ting when a collision is detected. The COL signal remains set for the duration of the collision.
相關PDF資料 |
PDF描述 |
|---|---|
| LU3X34FT | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網收發(fā)器) |
| LU3X51FT-J80 | Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網收發(fā)器) |
| LU3X54FTL | Quad-FET for 10Base-T/100Base-TX/FX(應用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網收發(fā)器) |
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網收發(fā)器) |
| LUC4AB01 | ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM)) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
發(fā)布緊急采購，3分鐘左右您將得到回復。