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參數(shù)資料
| 型號： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 25/54頁 |
| 文件大?。?/td> | 626K |
| 代理商： | LU3X32FT |
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Lucent Technologies Inc.
25
Preliminary Data Sheet
July 2000
LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Functional Description
(continued)
Reset Operation
The LU3X32FT can reset each port either by hardware or software. A hardware reset is accomplished by applying
a negative pulse, with a duration of at least 1 ms, to the RSTZ pin of the LU3X32FT during normal operation. A
software reset is activated by setting the RESET bit in the basic mode control register (bit 15, register 00h). This bit
is self-clearing and, when set, will return a value of 1 until the software reset operation has completed.
Both hardware and software reset operations initialize all registers to their default values. This process includes re-
evaluation of all hardware configurable registers.
Logic levels on several I/O pins are detected during the hardware and software reset period to determine the initial
functionality of each of the ports. Some of these pins are used as output ports after reset operation.
Care must be taken to ensure that the configuration setup will not interfere with normal operation. Dedicated con-
figuration pins can be tied to V
CC
or ground directly. Configuration pins multiplexed with logic level output functions
should be either weakly pulled-up or weakly pulled-down through resistors. Configuration pins multiplexed with
LED outputs should be set up with one of the following circuits shown in Figure 5. Note that the 10 k
resistor is
needed only for nondefault configuration.
5-7911(F)
Figure 5. Hardware RESET Configurations
PHY Address
During hardware reset, the logic level of the PHY address pins are latched into bits 4 through 1 of the PHY address
register, address 19h, respectively. Because the LU3X32FT implements two physical layers, the PHY address bit 0
is internally set to 0 for port 0 and 1 for port 1. This 5-bit address is used as the PHY address for serial manage-
ment interface communication. Note that initializing all configurable PHY addresses to zero automatically isolates
the MII interface of port 0.
Node/Repeater Mode Select
A logic 1 level on pins 57 or 110 during reset configures the port to function as a repeater. Otherwise, this device
will function in node mode.
Fiber Mode Select
A logic 1 level on pins 51 or 116 during reset configures the 100 Mbits/s section of the respective port for 100Base-
FX operation.
I/O PIN
I/O PIN
LOGIC 1 CONFIGURATION
LOGIC 0 CONFIGURATION
10 k
10 k
V
CC
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