參數(shù)資料
型號： LU3X32FT
廠商： Lineage Power
英文描述： Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
中文描述： 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網(wǎng)收發(fā)器）
文件頁數(shù)： 7/54頁
文件大?。?/td> 626K
代理商： LU3X32FT
Lucent Technologies Inc.
7
Preliminary Data Sheet
July 2000
LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Note: Many of these signals are dual-function pins. During reset, these pins may be pulled up or down (as shown in Figure 5) to configure
various options. The secondary function is shown in smaller
print and described in Table 5.
Table 5. PHY Address Configuration
100, 67
101, 66
102, 65
103, 64
TXD2[1:0]
TXD1[1:0]
TXD0[1:0]
TXCLK[1:0]
I
I
I
Transmit Data[2]
.
Transmit Data[1]
.
Transmit Data[0]
.
Transmit Clock
. This pin outputs during node mode
only. For 100 Mbits/s repeater mode, all transmit related
MII signals should be synchronized to 25 MHz clock on
XIN pin. See Table 8 for 10 Mbits/s repeater mode clock-
ing.
Carrier Sense/PHY Address [3]
. This output pin indi-
cates the carrier sense condition. It is only active on
receive while in repeater mode. See Table 5 for PHY[3]
description.
Collision/False Carrier Sense
. This output pin indi-
cates collision condition in node operation and indicates
false carrier sense condition in repeater mode. This out-
put is squelch jabber in 10 Mbits/s mode. See Table 5 for
PHY[4] description.
Management Data I/O
.
Management Data Clock
.
MII Enable
. A logic 0 on this pin tri-states all RX inter-
face signals of MII. This pin is intended to be used by the
repeater controller to selectively enable one of the PHYs
in the system. For node applications, this pin is ignored.
MDIO Interrupt (Active-Low)
. The MDIO interrupt pin
outputs a logic 0 pulse of 40 ns, synchronous to XIN,
whenever an unmasked interrupt condition is detected.
Refer to management registers 1Dh and 1Eh for inter-
rupt conditions. See Table 5 for PHY[2] description.
O
104, 63
CRS
/PHY[3]
[1:0]
I/O
109, 58
COL/FCRS
/PHY[4]
[1:0]
I/O
105, 62
115, 52
119, 48
MDIO[1:0]
MDC[1:0]
MIIENA[1:0]
I/O
I
I
84, 83
MDIOINTZ
/PHY[2]
[1:0]
I/O
Pin No.
Pin Name
PHY[0]
PHY[1][1:0]
PHY[2]
/MDIOINTZ
[1:0]
PHY[3]
/CRS
[1:0]
PHY[4]
/COL/FCRS
[1:0]
I/O
Pin Description
107, 60
84, 83
104, 63
109, 58
I
I/O
I/O
I/O
PHY Address [4:1]
. These 8 pins are detected during
powerup or reset to initialize the PHY address used for
MII management register interface. PHY address 00h
forces the PHY into MII isolate mode. PHY address pins
[4:2] have an internal 40 k
pull-down. PHY address [0]
is forced to 0 for port 0, and 1 for port 1. See Table 4 for
MDIOINTZ, CRS, COL, and FCRS descriptions.
Pin No.
Pin Name
I/O
Pin Description
Pin Descriptions
(continued)
Table 4. MII Interface
(continued)
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