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參數(shù)資料
| 型號(hào)： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬(wàn)位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁(yè)數(shù)： | 36/54頁(yè) |
| 文件大?。?/td> | 626K |
| 代理商： | LU3X32FT |
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LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
36
Lucent Technologies Inc.
Register Description
(continued)
Table 26. Config 100 Register (Per Port) [Register 18h]
Bit(s)
15
Name
BPSCR
Description
R/W
R/W
Default
Pin
1—Disable scrambler/descrambler.
0—Enable scrambler/descrambler.
This bit is initialized to the logic level of BPSCR
pin at powerup or reset.
1—Disable 4B/5B encoder/decoder.
0—Enable 4B/5B encoder/decoder.
This bit is initialized to the logic level of
BP4B5B pin at powerup or reset.
Reserved.
1—Pass unaligned data to MII.
0—Pass aligned data to MII.
This bit is initialized to the logic level of
BPALIGN pin at powerup or reset.
1—Enable FEFI.
0—Disable FEFI.
This bit enables/disables far-end fault indicator
function for 100Base-FX and 10Base-T opera-
tion. It is initialized to 1 if the logic level of the
FOSEL pin and the FEFI_EN/10HDEN/LEDFD
pin are both high at powerup or reset. After
reset, this bit is writable if and only if the
FOSEL register (bit 14 of register 17h) is set.
1—Enable CIM.
0—Disable CIM.
This bit enables/disables carrier integrity moni-
tor function for repeater operation.
It is initialized to 1 only if both NDRPTR and
CIMEN pins indicates logic 1 during powerup
or reset.
1—Force good link in 100 Mbits/s mode.
0—Normal operation.
Reserved.
1—Passes HALT symbols to the repeater core.
0—Normal operation.
1—Loads the scrambler seed.
0—Normal operation.
Setting this bit loads the user seed stored in
register 19h into the 100Base-X scrambler.
The content of this bit returns to 0 after the
loading process is completed and no transmit
is active.
1—Burst mode.
0—Normal operation.
Setting this bit expands the 722
μ
s scrambler
time-out period to 2,000
μ
s.
Reserved.
14
BP4B5B
R/W
Pin
13
12
Reserved
BPALIGN
RO
R/W
0h
Pin
11
Enable FEFI
R/W
Pin
10
Enable CIM
R/W
Pin
9
Force Good Link 100
R/W
0h
8:6
5
Reserved
Accept Halt
RO
R/W
00
0h
4
Load Seed
R/W, SC
0h
3
Burst Mode
R/W
0h
2:0
Reserved
RO
0h
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相關(guān)代理商/技術(shù)參數(shù) |
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| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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