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參數(shù)資料
| 型號： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 37/54頁 |
| 文件大?。?/td> | 626K |
| 代理商： | LU3X32FT |
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Lucent Technologies Inc.
37
Preliminary Data Sheet
July 2000
LU3X32FT Two-Port 3 V 10/100
Ethernet Transceiver TX/FX
Register Description
(continued)
Table 27. PHY Address Register (Per Port) [Register 19h]
Table 28. Config 10 Register (Per Port) [Register 1Ah]
Bit(s)
15:11
10:5
Name
Reserved
User Seed
Description
R/W
RO
R/W
Default
0h
21h
Reserved.
User-modifiable seed data. When the
load seed bit (bit 4 of register 18h) is set,
bits 10 through 0 of this register are
loaded into the 100Base-X scrambler. A
description is given in the symbol
encoder section.
These 4 bits, together with PHY address
0, store the part address used by the
serial management interface. PHY
address of 00000 has the special function
of isolating the part from the MII. These
bits are initialized to the logic levels of
PHY[4:1] pins at powerup or reset.
The least significant bit of PHY address.
After powerup or reset, this bit is initial-
ized to 0 for port 0 and 1 for port 1.
4:1
PHY Address 4 Through 1
R/W
Pin
0
PHY Address 0
R/W
0/1
Bit(s)
15
Name
Description
R/W
RO
Default
Pin
10 Mbits/s Serial Mode
1—10 Mbits/s serial mode.
0—10 Mbits/s nibble mode.
During 10Base-T operation, this bit deter-
mines whether the MII will be operating in nib-
ble mode or serial mode. It is initialized to 0h
at powerup and reset unless the logic level of
FOSEL pin is 0 and SER10 pin is 1.
1—Force 10 Mbits/s good link.
0—Normal operation.
Reserved.
1—Signal quality error test enabled.
0—Default SQE is disabled.
1—Low squelch level selected.
0—Normal squelch level selected.
1—Jabber function disabled.
0—Normal operation.
Reserved.
1—Powers down the PHY core completely.
The part comes out of this mode after a
reset is asserted and deasserted.
0—Normal operation.
Reserved.
1—Disable autopolarity function.
0—Enable autopolarity function.
Reserved.
14
Force 10 Meg Good Link
R/W
0h
13
12
Reserved
SQE_EN
R/W
R/W
1h
0h
11
Low Squelch Select
R/W
0h
10
Jabber Disable
R/W
0h
9:7
6
Reserved
Powerdown Mode
RO
R/W
0h
0h
5:4
3
Reserved
RO
R/W
0h
0h
Autopolarity Disable
2:0
Reserved
RO
0h
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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