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參數(shù)資料
| 型號(hào)： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 7/51頁 |
| 文件大?。?/td> | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
C2121-DAT-01F
7
December 2002
http://www.genesis-microchip.com
Revision History
Document
Description
Date
C2121-DAT-01A
Initial release
May 2002
C2121-DAT-01B
Corrected Pin out changes as follows:
o
Figure 2, gm2121 Pin out Diagram (Pin #102 to 116)
o
Table 2, RCLK PLL pins
o
Table 7, Power & Ground Pins for ADC Sampling Clock DDS
o
Table 8, Power & Ground Pins for Display Clock DDS
o
Table10, AVSS_OUT_LV_E pin
o
Table 6, one RESERVED pin and two RESERVED Pin name change to
VCO_LV & VBUFC
Corrected Pinout as follows:
Pins 88 to 97 changed from RESERVED to GPO [0..7]
Pins 38 and 39 changed to STI_TM1 and STI_TM2
Table 3, added GPO [0..7]
Table 6, removed RESERVED pins 88 to 97
Table 6, renamed pins 38 and 39 to STI_TM1 and STI_TM2 and added a clause that
these pins MUST be tied to GND.
Updated 4.14.4. with TCLK_SEL0, TCLK_SEL1 and DDC_PORT_SEL information.
These signals are new bootstrap configuration pins in gm2121
Updated 4.14.5 with the newly added GPO’s [0..7]
Updated 4.15 with the new bootstrap configuration pins
Table 20, updated DC Characteristics
Updated 4.14.4 and 4.15 with clarifications for the UART baud rates and DDC2Bi pin
selection options in standalone configuration
Changed Pin names:
o
RVDD to RVDD_3.3
o
CVDD to CVDD_2.5
o
AVDD_OUT_LV_E to AVDD_OUT_LV_E_2.5
o
AVDD_LV_E_ to AVDD_LV_E_2.5
o
AVDD_OUT_LV_O to AVDD_OUT_LV_O_2.5
o
AVDD_LV_O to AVDD_LV_O_2.5
o
AVDD_RPLL to AVDD_RPLL_3.3
o
VDD_DPLL to VDD_DPLL_3.3
o
AVDD_DDDS to AVDD_DDDS_3.3
o
VDD_DDDS to VDD_DDDS_3.3
o
AVDD_SSDS to AVDD_SSDS_3.3
o
VDD_SSDS to VDD_SSDS_3.3
o
VDD2_ADC to VDD2_ADC_2.5
o
VDD1_ADC to VDD1_ADC_2.5
o
AVDD_ADC to AVDD_ADC_3.3
o
AVDD_BLUE to AVDD_BLUE_3.3
o
AVDD_GREEN to AVDD_GREEN_3.3
o
AVDD_RED to AVDD_RED_3.3
Jun 2002
C2121-DAT-01C
Aug 2002
C2121-DAT-01D
C2121-DAT-01E
Added Section 4.2.2 – Correct Power Sequencing
Sep 2002
Oct 2002
Added the following note to Table 3 System Interface/GPIO signals GPIO4/UART_DI
and GPIO5/UART_DO: Add 10K Pull-up to VDD_3.3
Added note to Table 17 bootstrap signal HOST_PORT_EN (ROM_ADDR8)
Added note to Table 17 bootstrap signal OCM_ROM_CNFG(1) (ROM_ADDR14)
Updated Table 17 bootstrap signal DDC_PORT_SEL (ROM_ADDR12)
Documentation Fix: Pin Name Change GPIO16/HFS to GPIO16/HFSn
Added section 5.3 External ROM Interface Timing Requirements
C2121-DAT-01F
Dec 2002
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