參數(shù)資料
型號(hào)： GM2121
廠商： Electronic Theatre Controls, Inc.
英文描述： SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter
中文描述： SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器
文件頁(yè)數(shù)： 11/51頁(yè)
文件大?。?/td> 489K
代理商： GM2121
gm2121 Preliminary Data Sheet
C2121-DAT-01F
11
December 2002
http://www.genesis-microchip.com
3 GM2121Pin List
I/O Legend: A
= Analog,
I
= Input,
O
= Output,
P
= Power,
G
= Ground
Table 1.
Analog Input Port
Pin Name
No.
I/O
Description
AVDD_RED_3.3
136
AP
Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor to
AGND_RED pin on system board (as close as possible to the pin).
Positive analog input for Red channel.
Negative analog input for Red channel.
Analog ground for the red channel.
Must be directly connected to the system ground plane.
Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor to
AGND_GREEN pin on system board (as close as possible to the pin).
Positive analog input for Green channel.
Negative analog input for Green channel.
Analog ground for the green channel.
Must be directly connected to the system ground plane.
Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor to
AGND_BLUE pin on system board (as close as possible to the pin).
Positive analog input for Blue channel.
Negative analog input for Blue channel.
Analog ground for the blue channel.
Must be directly connected to the system ground plane.
Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes
band gap reference, master biasing and full-scale adjust. Must be bypassed with
decoupling capacitor to AGND_ADC pin on system board (as close as possible to the pin).
Analog test output for ADC Do not connect.
Analog ground for ADC analog blocks that are shared by all three channels. Includes band
gap reference, master biasing and full-scale adjust.
Must be directly connected to system ground plane.
Dedicated pad for substrate guard ring that protects the ADC reference system.
Must be directly connected to the system ground plane.
Digital GND for ADC clocking circuit.
Must be directly connected to the system ground plane
Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND1_ADC pin on system board (as close as possible to the pin).
Digital GND for ADC clocking circuit.
Must be directly connected to the system ground plane.
Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND2_ADC pin on system board (as close as possible to the pin).
ADC input horizontal sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
ADC input vertical sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
RED+
RED-
AGND_RED
135
134
133
AI
AI
AG
AVDD_GREEN_3.3
132
AP
GREEN+
GREEN-
AGND_GREEN
131
130
129
AI
AI
AG
AVDD_BLUE_3.3
128
AP
BLUE+
BLUE-
AGND_BLUE
127
126
125
AI
AI
AG
AVDD_ADC_3.3
124
AP
ADC_TEST
AGND_ADC
123
122
AO
AG
SGND_ADC
121
AG
GND1_ADC
120
G
VDD1_ADC_2.5
119
P
GND2_ADC
118
G
VDD2_ADC_2.5
117
P
HSYNC
101
I
VSYNC
100
I
Table 2.
RCLK PLL Pins
Pin Name
No I/O Description
AVDD_RPLL_3.3
104
AP
Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a
0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).
Analog ground for the Reference DDS PLL.
Must be directly connected to the system ground plane.
Reference clock (TCLK) from the 20.0MHz crystal oscillator (see Figure 4), or from single-
ended CMOS/TTL clock oscillator (see Figure 7). This is a 5V-tolerant input. See Table 12.
Crystal oscillator output.
Digital power for FCLK and RCLK PLLs. Connect to 3.3V supply.
Digital ground for FCLK and RCLK PLLs.
AVSS_RPLL
105
AG
TCLK
102
AI
XTAL
VDD_DPLL_3.3
VSS_DPLL
103
106
107
AO
P
G
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