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參數(shù)資料
| 型號： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 40/51頁 |
| 文件大?。?/td> | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
The UART is connected to pins GPIO4/UART_DI and GPIO5/UART_DO. gm2121 has serial-to-
parallel conversion hardware which is accessed by firmware.
Note: Install 10K
pull-ups on UART according to Table 3.
C2121-DAT-01F
40
December 2002
http://www.genesis-microchip.com
4.14.5 DDC2Bi Interface
The gm2121 also features hardware support for DDC2Bi communication over the DDC channel of the
analog input ports. The specification for the DDC2Bi standard can be obtained from VESA
(
www.vesa.org)
. The DDC2Bi port can be used as a factory debug port or for field programming. In
particular, the DDC2Bi port can be used to 1) read / write chip registers (see section 4.15 below), 2) read /
write to NVRAM (see section 4.13.1 above), and 3) read / write to FLASH ROM (see section 4.13.3
above).
For DDC2Bi communication over the analog VGA connector pins GPIO22/HCLK and GPIO16/HFSn
should be connected to the DDC clock and data pins of the analog DSUB15 VGA connector. gm2121
contains serial to parallel conversion hardware, that is then accessed by firmware for interpretation and
execution of the DDC2Bi command set. Bootstrap option ROM_ADDR12 (pin 142) is used to select the
pin pair to be used for DDC2Bi communication. This signal (named DDC_PORT_SEL) selects between
DDC2Bi interface or GPIO functions for pin pairs 8 (GPIO22/HCLK), 9 (GPIO16/HFSn) and 18
(GPIO15/DDC_SCL), 19 (GPIO14/DDC_SDA) for the internal standalone firmware. See the truth table
below for further details.
DDC2Bi
Pin pair
Pin number
(Port Function)
DDC_PORT_SEL = ’0’
ROM_ADDR12 (pin
142) pulled LOW
DDC_PORT_SEL = ’1’
ROM_ADDR12 (pin
142) pulled HIGH
Pin 8
(GPIO22/HCLK)
Pin 9
(GPIO16/HFSn)
Pin 18
(GPIO15/DDC_SCL)
Pin 19
(GPIO14/DDC_SDA)
GPIO22
HCLK
Pin pair
HFSn / HCLK
GPIO16
HFSn
DDC_SCL
GPIO15
Pin pair
DDC_SDA /
DDC_SCL
DDC_SDA
GPIO14
4.14.6 General Purpose Inputs and Outputs (GPIO’s)
The gm2121 has 23 general-purpose input/output (GPIO) and 8 general-purpose output (GPO) pins.
These are used by the OCM to communicate with other devices in the system such as keypad buttons,
NVRAM, LEDs, audio DAC, etc. Each GPIO has independent direction control, open drain enable, for
reading and writing. The GPO’s are shared with gm2121’s TEST_BUS. To activate these GPO’s set
TEST BUS_CONTROL (register 0x1E6) to 0x00 and TEST_BUS_EN (register 0x1E7 bit 2) to ‘1’, pins
88-97 can function as general-purpose outputs GPO0-7. Note that the GPIO pins have alternate
functionality as described in Table 16 below.
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