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參數(shù)資料
| 型號(hào)： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 49/51頁 |
| 文件大小： | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
C2121-DAT-01F
49
December 2002
http://www.genesis-microchip.com
5.3 External ROM Interface Timing Requirements
ROM_ADDR[15:0]
ROM_DATA[7:0]
ROM_OEn
MICRO_CLK
(internal)
Latched Data
(internal)
74
A0
74
A0
00F4
00F5
00F6
T
RC
T
ACC
T
OE
T
MICRO_CLK
Address Asserted
Data Latched
Figure 31.
External ROM Interface Timing Diagram
T
MICRO_CLK
= 1 / f
TCLK
= 1 / 24MHz = 41.6 ns (if 24MHz TCLK crystal is used)
MICRO_CLK is the internal MCU clock derived from TCLK and has the same frequency as TCLK. At the maximum
supported TCLK frequency (24MHz) the MICRO_CLK period is about 41ns.
The ROM data is latched on the third MICRO_CLK rising edge after the ADDRESS bus is asserted. Due to this
requirement, the external ROM should have a maximum access time of equal to or less than three TCLK periods (for
example, less than 123 ns when 24MHz TCLK crystal is used).
There are three criteria to be met for the external ROM interface timing (again, using 24MHz TCLK as a worst-case
example):
1. T
RC
= 4 x T
MIRCO_CLK
= 166.4 ns
2. T
ACCmax
≤
3 x T
MIRCO_CLK
= 124.8 ns
3. T
OE
≤
2 x T
MIRCO_CLK
= 83.2 ns
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