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參數(shù)資料
| 型號： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 19/51頁 |
| 文件大小： | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
Some attention must be given to the details of the oscillator circuit when used with a crystal resonator.
The PCB traces should be as short as possible. The value of C
load
that is specified by the manufacturer
should not be exceeded because of potential start up problems with the oscillator. Additionally, the crystal
should be a parallel resonate-cut and the value of the equivalent series resistance must be less then 90
Ohms.
C2121-DAT-01F
19
December 2002
http://www.genesis-microchip.com
4.1.2 Using an External Clock Oscillator
Another option for providing the reference clock is to use a single-ended external clock oscillator. When
the gm2121 is in reset, the state of the ROM_ADDR13 is sampled. If ROM_ADDR13 is pulled high by
connecting to VDD through a pull-up resistor (10K
recommended, 15K
maximum) then external
oscillator mode is enabled. In this mode the internal oscillator circuit is disabled and the external
oscillator signal that is connected to the TCLK pin is routed to an internal clock buffer. This is illustrated
in Figure 7.
Vdd
GND
Oscillator
Internal
Oscillator
Reset State Logic
ROM_ADDR13
XTAL
TCLK
14 to 24 MHz
Vdd
OSC_OUT
TCLK Distribution
Internal Pull Down
Resistor
~ 60 K
Disable
gm2121
102
103
141
External Oscillator Enable
10 K
Vdd
Figure 7.
Using an External Single-ended Clock Oscillator
Table 11.
TCLK Specification
Frequency
Jitter Tolerance
Rise Time (10% to 90%)
Maximum Duty Cycle
14 to 24 MHz
250 ps
5 ns
40-60
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