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參數(shù)資料
| 型號： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 43/51頁 |
| 文件大?。?/td> | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
C2121-DAT-01F
43
December 2002
http://www.genesis-microchip.com
Table 18.
Instruction Byte Map
Operation Mode
Bit
7 6 5 4 3 2 1 0
0 0 0 1 x x A9 A8
0 0 1 0 x x A9 A8
Description
Write Address Increment
Write Address No Increment
(for table loading)
Allows the user to write a single or multiple bytes to a specified starting
address location. A Macro operation will cause the internal address pointer to
increment after each byte transmission. Termination of the transfer will cause
the address pointer to increment to the next address location.
Allows the user to read multiple bytes from a specified starting address
location. A Macro operation will cause the internal address pointer to
increment after each read byte. Termination of the transfer will cause the
address pointer to increment to the next address location.
1 0 0 1 x x A9 A8
1 0 1 0 x x A9 A8
Read Address Increment
Read Address No Increment
(for table reading)
0 0 1 1 x x A9 A8
0 1 0 0 x x A9 A8
1 0 0 0 x x A9 A8
1 0 1 1 x x A9 A8
1 1 0 0 x x A9 A8
0 0 0 0 x x A9 A8
0 1 0 1 x x A9 A8
0 1 1 0 x x A9 A8
0 1 1 1 x x A9 A8
1 1 0 1 x x A9 A8
1 1 1 0 x x A9 A8
1 1 1 1 x x A9 A8
Reserved
Spare
No operation will be performed
4.16.2 2-wire Serial Protocol
The 2-wire protocol consists of a serial clock HCLK and bi-directional serial data line HFSn. The bus
master drives HCLK and either the master or slave can drive the HFSn line (open drain) depending on
whether a read or write operation is being performed. The gm2121 operates as a slave on the interface.
The 2-wire protocol requires each device be addressable by a 7-bit identification number. The gm2121 is
initialized on power-up to 2-wire mode by asserting bootstrap pins HOST_PROTOCOL=0 and the device
identification number on HOST_ADDR(6:0) on the rising edge of RESETn (see Table 17). This provides
flexibility in system configuration with multiple devices that can have the same address.
A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in the figure
below. A transfer is initiated (START) by a high-to-low transition on HFSn while HCLK is held high. A
transfer is terminated by a STOP (a low-to-high transition on HFSn while HCLK is held high) or by a
START (to begin another transfer). The HFSn signal must be stable when HCLK is high, it may only
change when HCLK is low (to avoid being misinterpreted as START or STOP).
ADDRESS BYTE
HFSn
1
2
3
7
8
9
HCLK
4
5
6
1
2
8
9
DATA BYTE
ACK
ACK
START
STOP
Receiver acknowledges by holding SDA low
R/W
A6
A1
A2
A3
A4
A5
A0
D6
D7
D0
Figure 28.
2-Wire Protocol Data Transfer
Each transaction on the HFSn is in integer multiples of 8 bits (i.e. bytes). The number of bytes that can be
transmitted per transfer is unrestricted. Each byte is transmitted with the most significant bit (MSB) first.
After the eight data bits, the master releases the HFSn line and the receiver asserts the HFSn line low to
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