- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385302 > GM2121 (Electronic Theatre Controls, Inc.) SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter PDF資料下載
參數(shù)資料
| 型號： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 48/51頁 |
| 文件大?。?/td> | 489K |
| 代理商： | GM2121 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁當(dāng)前第48頁第49頁第50頁第51頁
gm2121 Preliminary Data Sheet
5.2 Preliminary AC Characteristics
C2121-DAT-01F
48
December 2002
http://www.genesis-microchip.com
The following targeted specifications have been derived by simulation.
All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum operating
conditions used were:
T
DIE
= 0 to 125
°
C, Vdd = 2.35 to 2.65V, Process = best to worst, C
L
= 16pF for all outputs.
Table 21.
Maximum Speed of Operation
Clock Domain
Main Input Clock (TCLK)
ADC Clock (ACLK)
HCLK Host Interface Clock (6-wire protocol)
Input Format Measurement Clock (IFM_CLK)
Reference Clock (RCLK)
On-Chip Microcontroller Clock (OCM_CLK)
Display Clock (DCLK)
Max Speed of Operation
24 MHz ( 20.0MHz recommended)
162.5MHz
5 MHz
50MHz ( 20.0MHz recommended)
200MHz (200MHz recommended)
100 MHz
135 MHz
Table 22.
Display Timing and DCLK Adjustments
DP_TIMING ->
Tap 0
(default)
Min
(ns)
1.0
1.0
0.5
1.0
Tap 1
Tap 2
Tap 3
Max
(ns)
4.5
4.5
4.5
4.5
Min
(ns)
0.5
0.5
0.0
0.5
Max
(ns)
3.5
3.5
3.5
3.5
Min
(ns)
-0.5
-0.5
-1.0
-0.5
Max
(ns)
2.5
2.5
2.5
2.5
Min
(ns)
-1.5
-1.5
-2.0
-1.5
Max
(ns)
1.5
1.5
1.5
1.5
Propagation delay from DCLK to DA*/DB*
Propagation delay from DCLK to DHS
Propagation delay from DCLK to DVS
Propagation delay from DCLK to DEN
Note:
DCLK Clock Adjustments are the amount of additional delay that can be inserted in the DCLK path, in order to reduce the
propagation delay between DCLK and its related signals.
Table 23.
2-Wire Host Interface Port Timing
Parameter
Symbol
MIN
TYP
MAX
Units
SCL HIGH time
SCL LOW time
SDA to SCL Setup
SDA from SCL Hold
Propagation delay from SCL to SDA
T
SHI
T
SLO
T
SDIS
T
SDIH
T
SDO3
1.25
1.25
30
20
10
us
us
ns
ns
ns
150
Note
: The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) (ie 10ns / clock)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GM317 | 3- TERMINAL ADJUSTABLE REGULATOR |
| GM317TA3R | 3- TERMINAL ADJUSTABLE REGULATOR |
| GM317TA3T | 3- TERMINAL ADJUSTABLE REGULATOR |
| GM317TB3T | 3- TERMINAL ADJUSTABLE REGULATOR |
| GM5060 | GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GM2123 | 制造商:GTM 制造商全稱:GTM 功能描述:CMOS POSITIVE VOLTAGE REGULATOR |
| GM2125 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ANALOG INTER FACE XGA/SXGA ONPANEL LCD PANEL CONTROLLER |
| GM2126 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ANALOG INTERFACE ONPANEL SXGA LCD CONTROLLER WITH RSDS TRANSMITTER |
| GM215 | 制造商:GECKODRIVE 功能描述:CONTROLLER STEPPER MOTOR 13W 制造商:GECKODRIVE 功能描述:CONTROLLER, STEPPER MOTOR, 13W, No. of Phases:(Not Available), SVHC:No SVHC (20- |
| GM216 NJ BLACK | 制造商:Hirschmann Electronics GmbH & Co Kg 功能描述:CONNECTOR SOLENOID |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。