參數(shù)資料
型號(hào)： GM2121
廠商： Electronic Theatre Controls, Inc.
英文描述： SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter
中文描述： SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器
文件頁(yè)數(shù)： 44/51頁(yè)
文件大小： 489K
代理商： GM2121
gm2121 Preliminary Data Sheet
acknowledge receipt of the data. The master device generates the HCLK pulse during the acknowledge
cycle. The addressed receiver is obliged to acknowledge each byte that has been received.
C2121-DAT-01F
44
December 2002
http://www.genesis-microchip.com
The Write Address Increment and the Write Address No Increment operations allow one or multiple
registers to be programmed with only sending one start address. In Write Address Increment, the address
pointer is automatically incremented after each byte has been sent and written. The transmission data
stream for this mode is illustrated in Figure 29 below. The highlighted sections of the waveform represent
moments when the transmitting device must release the HFSn line and wait for an acknowledgement from
the gm2121 (the slave receiver).
ACK
ACK
ACK
OPERATION CODE
START
HFSn
HCLK
STOP
DEVICE ADDRESS
REGISTER ADDRESS
DATA
DATA
R/W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
9
A8
Two MSBs of register address
A9
Figure 29.
2-Wire Write Operations (0x1x and 0x2x)
The Read Address Increment (0x90) and Read Address No Increment (0xA0) operations are illustrated in
Figure 30. The highlighted sections of the waveform represent moments when the transmitting device
must release the HFSn line and waits for an acknowledgement from the master receiver.
Note that on the last byte read, no acknowledgement is issued to terminate the transfer.
DATA
DEVCEADDRESS
DATA
DATA
START
ACK
ACK
OPERATONCODE
START
HFSn
HCLK
STOP
DEVCEADDRESS
REGSTERADDRESS
RW ACK
RW ACK
ACK
Figure 30.
2-Wire Read Operation (0x9x and 0xAx)
Please note that in all the above operations the operation code includes two address bits, as described in
Table 18.
4.17 Miscellaneous Functions
4.17.1 Low Power State
The gm2121 provides a low power state in which the clocks to selected parts of the chip may be disabled (see
Table 20).
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