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參數(shù)資料
| 型號(hào)： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 31/51頁 |
| 文件大?。?/td> | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
4.9 Gamma LUT
C2121-DAT-01F
31
December 2002
http://www.genesis-microchip.com
The gm2121 provides an 8 to 10-bit look-up table (LUT) for each input color channel intended for
Gamma correction and to compensate for a non-linear response of the LCD panel. A 10-bit output results
in an improved color depth control. The 10-bit output is then dithered down to 8 bits (or 6 bits) per
channel at the display (see section 4.10.3 below). The LUT is user programmable to provide an arbitrary
transfer function. Gamma correction occurs after the zoom / shrink scaling block.
The LUT has bypass enable. If bypassed, the LUT does not require programming.
4.10 Display Output Interface
The Display Output Port provides data and control signals that permit the gm2121 to connect to a variety
of flat panel or CRT devices. The output interface is configurable for 18 or 24-bit RGB pixels, either
single or double pixel wide. All display data and timing signals are synchronous with the DCLK output
clock.
4.10.1 Display Synchronization
Refer to section 4.1 for information regarding internal clock synthesis.
The gm2121 supports the following display synchronization modes:
Frame Sync Mode:
The display frame rate is synchronized to the input frame or field rate.
This mode is used for standard operation.
Free Run Mode:
No synchronization. This mode is used when there is no valid input timing
(i.e. to display OSD messages or a splash screen) or for testing purposes. In free-run mode,
the display timing is determined only by the values programmed into the display window and
timing registers.
4.10.2 Programming the Display Timing
Display timing signals provide timing information so the Display Port can be connected to an external
display device. Based on values programmed in registers, the Display Output Port produces the
horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control signals, which are then
encoded into the LVDS data stream by the on-chip LVDS transmitter. The figure below provides the
registers that define the output display timing.
Horizontal values are programmed in single pixel increments relative to the leading edge of the horizontal
sync signal. Vertical values are programmed in line increments relative to the leading edge of the vertical
sync signal.
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