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參數(shù)資料
| 型號： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 28/51頁 |
| 文件大小： | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
4.5.2 Horizontal and Vertical Measurement
C2121-DAT-01F
28
December 2002
http://www.genesis-microchip.com
The IFM is able to measure the horizontal period and active high pulse width of the HSYNC signal, in
terms of the selected clock period (either TCLK or RCLK/4.). Horizontal measurements are performed on
only a single line per frame (or field). The line used is programmable. It is able to measure the vertical
period and VSYNC pulse width in terms of rising edges of HSYNC.
Once enabled, measurement begins on the rising VSYNC and is completed on the following rising
VSYNC. Measurements are made on every field / frame until disabled.
4.5.3 Format Change Detection
The IFM is able to detect changes in the input format relative to the last measurement and then alert both
the system and the on-chip microcontroller. The microcontroller sets a measurement difference threshold
separately for horizontal and vertical timing. If the current field / frame timing is different from the
previously captured measurement by an amount exceeding this threshold, a status bit is set. An interrupt
can also be programmed to occur.
4.5.4 Watchdog
The watchdog monitors input VSYNC / HSYNC. When any HSYNC period exceeds the programmed
timing threshold (in terms of the selected IFM_CLK), a register bit is set. When any VSYNC period
exceeds the programmed timing threshold (in terms of HSYNC pulses), a second register bit is set. An
interrupt can also be programmed to occur.
4.5.5 Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only)
The IFM has the ability to perform field decoding of interlaced inputs to the ADC. The user specifies start
and end values to outline a “window” relative to HSYNC. If the VSYNC leading edge occurs within this
window, the IFM signals the start of an ODD field. If the VSYNC leading edge occurs outside this
window, an EVEN field is indicated (the interpretation of odd and even can be reversed). The window
start and end points are selected from a predefined set of values.
HS
window
VS - even
VS - odd
Window
Start
Window End
Figure 18.
ODD/EVEN Field Detection
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