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參數(shù)資料
| 型號： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 24/51頁 |
| 文件大?。?/td> | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
C2121-DAT-01F
24
December 2002
http://www.genesis-microchip.com
Table 13.
ADC Characteristics
Track & Hold Amp Bandwidth
MIN
TYP
MAX
290 MHz Guaranteed by design. Note that the Track &
Hold Amp Bandwidth is programmable. 290
MHz is the maximum setting.
0.90 V
Measured at ADC Output.
Independent of full scale RGB input.
Measured at ADC Output.
162.5 MHz
+/-0.9 LSB Fs = 135 MHz
Guaranteed by test.
Fs =135 MHz
NOTE
Full Scale Adjust Range at RGB Inputs
Full Scale Adjust Sensitivity
0.55 V
+/- 1 LSB
Zero Scale Adjust Sensitivity
Sampling Frequency (Fs)
Differential Non-Linearity (DNL)
No Missing Codes
Integral Non-Linearity (INL)
Channel to Channel Matching
+/- 1 LSB
+/-0.5 LSB
+/- 1.5 LSB
+/- 0.5 LSB
10 MHz
Note that input formats with resolutions or refresh rates higher than that supported by the LCD panel are
supported as recovery modes only. This is called RealRecovery. For example, it may be necessary to
shrink the image. This may introduce image artifacts. However, the image is clear enough to allow the
user to change the display properties.
The gm2121 ADC has a built in clamp circuit for AC-coupled inputs. By inserting series capacitors
(about 10 nF), the DC offset of an external video source can be removed. The clamp pulse position and
width are programmable.
4.3.3 Clock Recovery Circuit
The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used to sample
analog RGB data (IP_CLK or source clock). This circuit is locked to HSYNC of the incoming video
signal.
Patented digital clock synthesis technology makes the gm2121 clock circuits resistant to
temperature/voltage drift. Using DDS (Direct Digital Synthesis) technology, the clock recovery circuit
can generate any IP_CLK clock frequency within the range of 10MHz to 165MHz.
Window
Capture
SDDS
ADC
R
G
B
IPCLK
HSYNC
HSYNC
(delayed)
24
Phase
Image Phase
Measurement
Figure 12.
gm2121 Clock Recovery
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