參數(shù)資料
型號(hào)： GM2121
廠商： Electronic Theatre Controls, Inc.
英文描述： SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter
中文描述： SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器
文件頁(yè)數(shù)： 21/51頁(yè)
文件大?。?/td> 489K
代理商： GM2121
gm2121 Preliminary Data Sheet
5. ADC Domain Clock (ACLK). Max = 165MHz.
C2121-DAT-01F
21
December 2002
http://www.genesis-microchip.com
The clock selection for each domain as shown in the figure below is controlled using the
CLOCK_CONFIG registers (index 0x03 and 0x04).
SCLK
SENSE_ACLK
IP_CLK
DCLK
IP_CLK
DP_CLK
SCLK
ACLK
OCM_CLK
RCLK/2
TCLK
IFM_CLK
TCLK
RCLK/4
Figure 9.
On-chip Clock Domains
4.2 Chip Initialization
4.2.1 Hardware Reset
Hardware Reset is performed by holding the RESETn pin low for a minimum of 1
μ
s. A TCLK input (see
Clock Options above) must be applied during and after the reset. When the reset period is complete and
RESETn is de-asserted, the power-up sequence is as follows:
1. Reset all registers of all types to their default state (this is 00h unless otherwise specified in the
gm2121 Register Listing).
2. Force each clock domain into reset. Reset will remain asserted for 64 local clock domain cycles
following the de-assertion of RESETn.
3. Operate the OCM_CLK domain at the TCLK frequency.
4. Preset the RCLK PLL to output ~200MHz clock (assumes 20.0MHz TCLK crystal frequency).
5. Wait for RCLK PLL to Lock. Then, switch the OCM_CLK domain to operate from the bootstrap
selected clock.
6. If a pull-up resistor is installed on ROM_ADDR9 pin (see Table 17), then the OCM becomes active
as soon as OCM_CLK is stable. Otherwise, the OCM remains in reset until OCM_CONTROL
register (0x22) bit 1 is enabled.
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