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參數(shù)資料
| 型號： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 20/51頁 |
| 文件大小： | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
4.1.3 Clock Synthesis
C2121-DAT-01F
20
December 2002
http://www.genesis-microchip.com
The gm2121 synthesizes all additional clocks internally as illustrated in Figure 8 below. The synthesized
clocks are as follows:
1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is derived from
the TCLK/XTAL pad input.
2. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) using TCLK as the reference.
3. Input Source Clock (SCLK) synthesized by Source DDS (SDDS) PLL using input HSYNC as the
reference. The SDDS internal digital logic is driven by RCLK.
4. Display Clock (DCLK) synthesized by Destination DDS (DDDS) PLL using IP_CLK as the
reference. The DDDS internal digital logic is driven by RCLK.
5. Half Reference Clock (RCLK/2) is the RCLK (see 2, above) divided by 2. Used as OCM_CLK
domain driver.
6. Quarter Reference Clock (RCLK/4) is the RCLK (see 2, above) divided by 4. Used as alternative
clock (faster than TCLK) to drive IFM.
7. ADC Output Clock (SENSE_ACLK) is a delay-adjusted ADC sampling clock, ACLK. ACLK is
derived from SCLK.
RCLK
PLL
SDDS
DDDS
/2
/4
SCLK
DCLK
RCLK/2
RCLK/4
HSYNC
IP_CLK
TCLK
Figure 8.
Internally Synthesized Clocks
The on-chip clock domains are selected from the synthesized clocks as shown in Figure 9 below. These
include:
1. Input Domain Clock (IP_CLK). Max = 165MHz
2. Host Interface and On-Chip Microcontroller Clock (OCM_CLK). Max = 100MHz
3. Filter and Display Pixel Clock (DP_CLK). Max = 135MHz
4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz
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