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參數(shù)資料
| 型號： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 22/51頁 |
| 文件大?。?/td> | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
4.2.2 Correct Power Sequencing
C2121-DAT-01F
22
December 2002
http://www.genesis-microchip.com
The system designer must ensure that the 2.5V CVDD and 3.3V RVDD power supply rails power up in
the correct sequence. That is, at any time during the power-up sequence the actual voltage of the 3.3V
RVDD power supply should always be equal to or higher than the actual voltage of the 2.5V CVDD
power supply. In mathematical terms, V
RVDD
>= V
CVDD
at all times. This is illustrated in Figure 10.
In addition, the system designer must ensure that the 2.5V core VDD supply must be active for at least
1ms before the rising edge of the chip RESETn signal during the chip power-up sequence. The rising
edge of RESETn signal is used to latch the bootstrap configurations, so its correct timing relationship to
the core VDD is critical for correct chip operation.
RVDD (3.3V)
CVDD (2.5V)
Time
Voltage
V
RVDD-CVDD
(t)
RESETn
Time
Voltage
0V
T
CVDD->RESETn
t
Figure 10.
Correct Power Sequencing
Parameter
Min
Typ
Max
V
RVDD-CVDD
(for all t>0)
0V
T
CVDD->RESETn
1ms
4.3 Analog to Digital Converter
The gm2121 chip has three ADC’s (analog-to-digital converters), one for each color (red, green, and
blue).
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