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參數資料
| 型號： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數： | 25/51頁 |
| 文件大?。?/td> | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
4.3.4 Sampling Phase Adjustment
C2121-DAT-01F
25
December 2002
http://www.genesis-microchip.com
The programmable ADC sampling phase is adjusted by delaying the HSYNC input to the SDDS. The
accuracy of the sampling phase is checked and the result read from a register. This feature enables
accurate auto-adjustment of the ADC sampling phase.
4.3.5 ADC Capture Window
Figure 13 below illustrates the capture window used for the ADC input. In the horizontal direction the
capture window is defined in IP_CLKs (equivalent to a pixel count). In the vertical direction it is defined
in lines.
All the parameters beginning with “Source” are programmed gm2121 registers values. Note that the input
vertical total is solely determined by the input and is not a programmable parameter.
Capture Window
Source Width
Source
Hstart
Source Horizontal Total (pixels)
S
V
S
H
I
Reference
Point
Figure 13.
ADC Capture Window
The Reference Point marks the leading edge of the first internal HSYNC following the leading edge of an
internal VSYNC. Both the internal HSYNC and the internal VSYNC are derived from external HSYNC
and VSYNC inputs.
Horizontal parameters are defined in terms of single pixel increments relative to the internal horizontal
sync. Vertical parameters are defined in terms of single line increments relative to the internal vertical
sync.
For ADC interlaced inputs, the gm2121 may be programmed to automatically determine the field type
(even or odd) from the VSYNC/HSYNC relative timing. See Input Format Measurement, Section 4.4.
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