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參數(shù)資料
| 型號： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁數(shù)： | 42/51頁 |
| 文件大?。?/td> | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
C2121-DAT-01F
42
December 2002
http://www.genesis-microchip.com
Signal Name
Pin Name
Description
TCLK_SEL1
TCLK_SEL0
ROM_ADDR11
ROM_ADDR10
Selects the for the standalone firmware UART baud rate depending on the frequency of the TCLK crystal
(TCLK_SEL1, TCLK_SEL0)
00 = 115.2 KBaud (for TCLK = 14.3 MHz)
01 = 57.6 KBaud (for TCLK = 20 MHz)
10 = 57.6 KBaud (for TCLK = 24 MHz)
11 = 57.6 KBaud (for TCLK = 14.3 MHz)
Selects reference clock source (refer to Figure 7):
0 = XTAL and TCLK pins are connected to a crystal oscillator.
1 = TCLK input is driven with a single-ended TTL/CMOS clock oscillator.
Together with OCM_CONTROL register (0x22) bit 4, this bit selects internal/external ROM configuration.
0 = All 48K of ROM is internal.
1 = All 48K of ROM is in external ROM using ROM_ADDR15:0 address outputs if
register 0x22 bit 4 is 0. If register 0x22 bit 4 is 1, 0-32K ROM is internal, and
32K~48K ROM is external using ROM_ADDR13:0 address outputs.
Note: When booting from internal ROM (standalone configuration) the embedded firmware checks for a
signature in external ROM (values 0x89, 0xAB, 0xCD, 0xEF at addresses 0xFFFC, 0xFFFD, 0xFFFE,
0xFFFF) and if present then OCM begins executing from address 0x0000 of external ROM (i.e. full-custom
configuration).
Sets the polarity of the PBIAS signal after the RESET sequence. This is to prevent flashing during power
up, for panels with active LOW panel enable signal.
0 = PBIAS set to LOW after RESET
1 = PBIAS set to HIGH after RESET
OSC_SEL
ROM_ADDR13
OCM_ROM_CNFG(1)
ROM_ADDR14
PBIAS_POL
ROM_ADDR15
4.16 Host Interface
gm2121 contains many internal registers that control its operation. These are described in the gm2121
Register Listing (C2121-DSL-01).
A serial host interface is provided to allow an external device to peek and poke registers in the gm2121.
This is done using a 2-wire serial protocol. Note that 2-wire host interface requires bootstrap settings as
described in Table 17.
An arbitration mechanism ensures that register accesses from the OCM and the 2-wire host interface port
are always serviced (time division multiplexing).
4.16.1 Host Interface Command Format
Transactions on the 2-wire host protocol occurs in integer multiples of bytes (i.e. 8 bits or two nibbles
respectively). These form an instruction byte, a device register address and/or one or more data bytes.
This is described in Table 18.
The first byte of each transfer indicates the type of operation to be performed by the gm2121. The table below
lists the instruction codes and the type of transfer operation. The content of bytes that follow the instruction byte
will vary depending on the instruction chosen. By utilizing these modes effectively, registers can be quickly
configured.
The two LSBs of the instruction code, denoted 'A9' and 'A8' in Table 18 below, are bits 9 and 8 of the
internal register address respectively. Thus, they should be set to ‘00’ to select a starting register address
of less than 256, ‘01’ to select an address in the range 256 to 511, and '10' to select an address in the range
512 to 767. These bits of the address increment in Address Increment transfers. The unused bits in the
instruction byte, denoted by 'x', should be set to ‘1’.
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