
gm2121 Preliminary Data Sheet
C2121-DAT-01F
5
December 2002
http://www.genesis-microchip.com
Table 1.
Analog Input Port................................................................................................................11
Table 2.
RCLK PLL Pins ..................................................................................................................11
Table 3.
System Interface and GPIO Signals....................................................................................12
Table 4.
Display Output Port.............................................................................................................13
Table 5.
Parallel ROM Interface Port................................................................................................13
Table 6.
Reserved Pins
...................................................................................................................14
Table 7.
Power and Ground Pins for ADC Sampling Clock DDS....................................................14
Table 8.
Power and Ground Pins for Display Clock DDS ................................................................14
Table 9.
I/O Power and Ground Pins.................................................................................................15
Table 10.
Power and Ground Pins for LVDS Transmitter..............................................................15
Table 11.
TCLK Specification ........................................................................................................19
Table 12.
Pin Connection for RGB Input with HSYNC/VSYNC...................................................23
Table 13.
ADC Characteristics........................................................................................................24
Table 14.
Supported LVDS 24-bit Panel Data Mapping.................................................................34
Table 15.
Supported LVDS 18-bit Panel Data Mapping.................................................................34
Table 16.
gm2121 GPIOs and Alternative Functions .....................................................................41
Table 17.
Bootstrap Signals.............................................................................................................41
Table 18.
Instruction Byte Map.......................................................................................................43
Table 19.
Absolute Maximum Ratings............................................................................................46
Table 20.
DC Characteristics...........................................................................................................47
Table 21.
Maximum Speed of Operation........................................................................................48
Table 22.
Display Timing and DCLK Adjustments........................................................................48
Table 23.
2-Wire Host Interface Port Timing .................................................................................48