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| 型號(hào)： | GM2121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SXGA LCD Monitor Controller with Integrated Analog Interface and Dual LVDS Transmitter |
| 中文描述： | SXGA液晶顯示器控制器集成模擬接口和雙路LVDS發(fā)送器 |
| 文件頁(yè)數(shù)： | 14/51頁(yè) |
| 文件大?。?/td> | 489K |
| 代理商： | GM2121 |
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gm2121 Preliminary Data Sheet
C2121-DAT-01F
14
December 2002
http://www.genesis-microchip.com
Table 6.
Reserved Pins
Pin Name
No I/O Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VBUFC
VCO_LV
STI_TM1
STI_TM2
80
81
82
83
84
85
86
87
112
45
38
39
O
O
O
O
O
O
O
O
O
O
I
I
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. MUST be tied to GND
For test purposes only. MUST be tied to GND
Table 7.
Power and Ground Pins for ADC Sampling Clock DDS
Pin Name
No I/O Description
AVDD_SDDS_3.3
113
AP
Analog power for the Source DDS. Connect to 3.3V supply.
Must be bypassed with a 0.1uF capacitor to AVSS_SDDS pin
(as close to the pin as possible).
Analog ground for the Source DDS.
Must be directly connected to the system ground.
Digital power for the Source DDS. Connect to 3.3V supply.
Digital ground for the Source DDS.
AVSS_SDDS
114
AG
VDD_SDDS_3.3
VSS_SDDS
115
116
P
G
Table 8.
Power and Ground Pins for Display Clock DDS
Pin Name
No I/O Description
AVDD_DDDS_3.3
108
AP
Analog power for Destination DDS. Connect to 3.3V supply.
Must be bypassed with a 0.1uF capacitor to AVSS_DDDS pin
(as close to the pin as possible).
Analog ground for Destination DDS.
Must be directly connected to the system ground plane.
Digital power for the Destination DDS. Connect to 3.3V supply.
Digital ground for the Destination DDS.
AVSS_DDDS
109
AG
VDD_DDDS_3.3
VSS_DDDS
110
111
P
G
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