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參數(shù)資料
| 型號： | EVAL-ADAU1446EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 84/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1446 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1446 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板，軟件 |
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ADAU1445/ADAU1446
Rev. A | Page 85 of 92
APPLICATIONS INFORMATION
07
69
6-
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6
LAYOUT RECOMMENDATIONS
Parts Placement
All 100 nF bypass capacitors, which are recommended for every
analog, digital, and PLL power-ground pair, should be placed as
close to the ADAU1445/ADAU1446 as possible. The AVDD,
DVDD, PVDD, and IOVDD supply signals on the board should
each be bypassed with an additional single bulk capacitor (10 μF
to 47 μF).
All traces in the crystal oscillator circuit (Figure 9) should be
kept as short as possible to minimize stray capacitance. There
should not be any long board traces connected to crystal
oscillator circuit components because such traces may affect
crystal startup and operation.
Figure 61. Exposed Pad Layout Example—Top View
PLL Loop Filter
The single resistor and two capacitors in the PLL loop filter
should be connected to the PLL_FILT and PVDD pins with
short traces to minimize jitter.
Grounding
Power Supply Bypass Capacitors
A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.
Each power supply pin should be bypassed to its nearest
appropriate ground pin with a single 100 nF capacitor. The
connections to each side of the capacitor should be as short as
possible, and the trace should stay on a single layer with no vias.
For maximum effectiveness, the capacitor should preferably be
located either equidistant from the power and ground pins or,
when equidistant placement is not possible, slightly closer to the
power pin. Thermal connections to the planes should be made
on the far side of the capacitor.
Exposed Pad PCB Design
The ADAU1445 package includes an exposed pad for improved
heat dissipation. When designing a board for such a package,
special consideration should be given to the following:
A copper layer equal in size to the exposed pad should be
on all layers of the board, from top to bottom, and should
connect somewhere to a dedicated copper board layer (see
POWER GROUND
TO GROUND
TO POWER
CAPACITOR
07
69
6-
0
61
Vias should be placed to connect all layers of copper, allowing
for efficient heat and energy conductivity. For an example,
see Figure 61, which has 16 vias arranged in a 4 × 4 grid in
the pad area.
0
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6-
0
67
TOP
POWER
GROUND
BOTTOM
COPPER SQUARES
VIAS
Figure 62. Recommended Power Supply Bypass Capacitor Layout
Figure 60. Exposed Pad Layout Example—Side View
EOS/ESD Protection
Although the ADAU1445/ADAU1446 have robust internal
protection circuitry against overvoltages and electrostatic
discharge, an external transient voltage suppressor (TVS) is
recommended for all systems to prevent damage to the IC.
Examples can be found in the AN-311 Application Note on the
Analog Devices website.
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