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參數(shù)資料
| 型號(hào)： | EVAL-ADAU1446EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 61/92頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1446 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1446 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板，軟件 |
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ADAU1445/ADAU1446
Rev. A | Page 64 of 92
S/PDIF MODES AND SETTINGS
Table 52. Addresses of S/PDIF Modes Registers
Address
Name
Read/Write
Word Length
Decimal
Hex
57536
E0C0
S/PDIF receiver—read
auxiliary output
16 bits (2 bytes)
57537
E0C1
S/PDIF transmitter—
on/off switch
16 bits (2 bytes)
57538
E0C2
S/PDIF read channel
status, Byte 0
16 bits (2 bytes)
57539
E0C3
S/PDIF read channel
status, Byte 1
16 bits (2 bytes)
57540
E0C4
S/PDIF read channel
status, Byte 2
16 bits (2 bytes)
57541
E0C5
S/PDIF read channel
status, Byte 3
16 bits (2 bytes)
57542
E0C6
S/PDIF read channel
status, Byte 4
16 bits (2 bytes)
57543
E0C7
S/PDIF word length
control
16 bits (2 bytes)
57544
E0C8
Auxiliary outputs—set
enable mode
16 bits (2 bytes)
57545
E0C9
S/PDIF lock bit
detection
16 bits (2 bytes)
57546
E0CA
Set hot enable
16 bits (2 bytes)
57547
E0CB
Read enable auxiliary
output
16 bits (2 bytes)
57548
E0CC
S/PDIF loss-of-lock
behavior
16 bits (2 bytes)
S/PDIF Receiver—Read Auxiliary Output Register
(Address 0xE0C0)
Table 53. Bit Descriptions of Register 0xE0C0
Bit Position
Readback Data
[15]
User data (read only)
[14]
Channel status (read only)
[13]
Block start (read only)
[12]
Virtual LRCLK (read only)
[11:8]
Reserved (read only)
[7:6]
Validity bits (read only)
[5:0]
Reserved
This is a read-only register. It allows the S/PDIF auxiliary
output (including channel status, user data, and validity bit)
to be read.
S/PDIF Transmitter—On/Off Switch Register
(Address 0xE0C1)
Table 54. Bit Descriptions of Register 0xE0C1
Bit
Position
Description
Default
[15:1]
Reserved
[0]
S/PDIF transmitter—on/off switch
0
0 = S/PDIF transmitter disabled
1 = S/PDIF transmitter enabled
This is a single-bit register. Setting Bit 0 to 1 switches the
S/PDIF transmitter on; setting it to 0 switches the transmitter
off for power savings.
S/PDIF Read Channel Status Register, Bytes[4:0]
(Address 0xE0C2 to Address 0xE0C6)
Table 55. Addresses of S/PDIF Read Channel Status Register
Address
Register
Decimal
Hex
57538
E0C2
Byte 0
57539
E0C3
Byte 1
57540
E0C4
Byte 2
57541
E0C5
Byte 3
57542
E0C6
Byte 4
An S/PDIF stream contains channel status bits (after the audio
bits), which contain information such as sample rates, word
lengths, and time stamps. The full channel status information
contained in the stream is 24 bytes wide for each channel (that
is, 48 bytes in total). The ADAU1445/ADAU1446 make the first
five bytes of the left channel available through I2C/SPI.
S/PDIF Word Length Control Register (Address 0xE0C7)
Table 56. Bit Descriptions of Register 0xE0C7
Bit
Position
Description
Default
[15:2]
Reserved
[1:0]
Word length
00
00 = 24 bit
01 = 20 bit
10 = 16 bit
11 = as decoded from the S/PDIF channel
status bits
The word length of the audio data decoded from the S/PDIF
stream can be controlled using this register. Setting Bits[1:0] to 11 is
useful in cases where the S/PDIF stream can come from either a
CD or a DVD. From a CD the word length is 16 bits, and from a
DVD the word length is 24 bits. This information is contained in
the channel status bits and can be used to automatically ignore
the least significant byte if required.
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