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| 型號： | EVAL-ADAU1446EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1446 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1446 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板，軟件 |
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ADAU1445/ADAU1446
Rev. A | Page 40 of 92
selector (that is, the 18:2 multiplexer) allows each serial output
port to clock from any available clock domain. In master mode,
the clock domain selector is bypassed, and the assignments
described in Table 26 are used.
Table 26. Output Clock Domain Assignments in Master Mode
Data Pin
Clock Pins
SDATA_OUT0
LRCLK9, BCLK9
SDATA_OUT1
LRCLK10, BCLK10
SDATA_OUT2
LRCLK11, BCLK11
SDATA_OUT3
LRCLK3, BCLK3
SDATA_OUT4
LRCLK4, BCLK4
SDATA_OUT5
LRCLK5, BCLK5
SDATA_OUT6
LRCLK6, BCLK6
SDATA_OUT7
LRCLK7, BCLK7
SDATA_OUT8
LRCLK8, BCLK8
The maximum number of audio channels that can be output
from SigmaDSP is 24. The serial output ports must be set in a
way that respects this (for example, two TDM16 streams is not a
valid entry).
All data is processed in twos complement, MSB-first format,
and the left channel always precedes the right channel.
SERIAL OUTPUT PORT MODES AND SETTINGS
Each of the nine serial output ports is controlled by setting an
individual 2-byte word in the serial output mode register for
each port (see Table 27 for the register addresses). Each serial
data signal can be set to use any of the nine clock domains
(slave mode) or an internally generated LRCLK signal at
fS,NORMAL, fS,DUAL, or fS,QUAD. The default value for each serial port
on reset is set to TDM2, I2S, 24-bit, negative LRCLK and BCLK
polarity, slave mode using a 50% duty cycle LRCLK clock signal
(as opposed to a synchronization pulse). This configuration
corresponds to a setting of 0x3C00. The serial data uses its
corresponding clock domain (for example, SDATA3 uses
LRCLK3 and BCLK3).
Restrictions
When the device is in MOST mode, the MSB position of the
serial data is delayed by one bit clock from the start of the frame
(I2S position) and the data width is restricted to 16 bits.
When in MSB delay-by-12 mode, the serial data can be 16 or
20 bits wide (not 24 bits). When in MSB delay-by-16 mode, the
serial data can only be 16 bits wide.
For information on TDM capabilities, refer to Table 16.
SERIAL
OUTPUT
PORTS
(×9)
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
SDATA_OUT8
DEDICATED
OUTPUT
CLOCK DOMAINS
(×3)
9 TO 11
BCL
K9/
L
RCL
K9
B
C
LK
1
0
/LR
C
LK
1
0
B
C
LK
1
/LR
C
LK
1
ASSIGNABLE
INPUT/OUTPUT
CLOCK DOMAINS
(×6)
3 TO 8
BCL
K3/
L
RCL
K3
BCL
K4/
L
RCL
K4
BCL
K5/
L
RCL
K5
BCL
K6/
L
RCL
K6
BCL
K7/
L
RCL
K7
BCL
K8/
L
RCL
K8
4:2
TO SERIAL
INPUT PORTS
3 TO 8
(×6)
18:2
(×9)
CLOCK PAD
MULTIPLEXERS
CLOCK DOMAIN
SELECTOR
3
4
5
6
7
8
9
10 11
2
07
69
6-
0
34
Figure 33. Output Serial Port Clock Multiplexing
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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