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| 型號： | EVAL-ADAU1446EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 60/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1446 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1446 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板，軟件 |
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ADAU1445/ADAU1446
Rev. A | Page 63 of 92
S/PDIF RECEIVER AND TRANSMITTER
The ADAU1445/ADAU1446 each feature a set of on-chip
S/PDIF data ports, which can be wired directly to transmitters
and receivers for easy interfacing to other S/PDIF-compatible
equipment.
S/PDIF Receiver
The S/PDIF input port is designed to accept both TTL and
bipolar signals, provided there is an ac coupling capacitor on
the input pin of the chip. Because the S/PDIF input data will
most likely be asynchronous to the DSP core, it must be routed
through an ASRC.
The S/PDIF ports work with sampling rates between 32 kHz
and 108 kHz.
S/PDIF streams contain more than just audio data, including
user data, channel status, validity bit, virtual LRCLK, and block
start. The receiver decodes audio data and sends it to the ASRCs
and DSP core, but the remaining data passes through directly to
the transmitter. This ensures that any user data is unaltered at
the output and is reintegrated into the audio stream.
In the ADAU1445/ADAU1446, clock recovery is entirely
digital. As a result, the ADAU1445/ADAU1446 have better
protection against clock jitter.
The ADAU1445/ADAU1446 S/PDIF ports are designed to meet
the following AES and EBU specifications: a jitter of 0.25 UI p-p
at 8 kHz and above, a jitter of 10 UI p-p below 200 Hz, and a
minimum signal voltage of 200 mV.
To transmit data, the S/PDIF output must be turned on. This is
accomplished by writing an activation bit to the S/PDIF transmitter
on/off register. More information can be found in the Enable
S/PDIF to I2S Output section and the S/PDIF Transmitter—
Outputting to the Multipurpose Pins
It is possible to send S/PDIF data from the receiver directly to
output on the MP pins. This mode is activated in Register 0xE241
(see the Enable S/PDIF to I2S Output section). The pin assignment
of signals is shown in Table 51.
Table 51. S/PDIF to MP Pin Assignments
Pin1
Group
Signal
MP4
2
Validity bit
MP5
2
User data
MP6
2
Channel select
MP7
2
Block start
MP8
2
Virtual LRCLK
MP9
1
SDATA
MP10
1
BCLK
MP11
1
LRCLK
1 The MP0 to MP3 pins are not applicable and can be used normally.
There are two groups of signals, each of which can be activated
and deactivated independent from one another. All unused MP
pins function normally.
S/PDIF Transmitter
The S/PDIF transmitter outputs two channels of audio data
directly from the DSP core at the core rate. It does not preserve
or output any additional nonaudio information encoded in the
S/PDIF input stream.
S/PDIF
RECEIVER
I2S
CONVERTER
ASRCs
DSP CORE
S/PDIF
TRANSMITTER
AUDIO
AND
DATA
BCLK
LRCLK
SDATA
DATA BITS
MASTER
MODE
SPDIFO
SPDIFI
MP PINS
5
07
69
6-
05
4
Figure 53. S/PDIF Receiver and Transmitter
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