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| 型號： | EVAL-ADAU1446EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1446 |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1446 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板，軟件 |
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ADAU1445/ADAU1446
Rev. A | Page 23 of 92
VOLTAGE REGULATOR
The digital supply voltage of the ADAU1445/ADAU1446 must
be set to 1.8 V. The chip includes an on-board voltage regulator
that allows the device to be used in systems where a 1.8 V supply is
not available but a 3.3 V supply is. The only external components
needed for this are a PNP transistor and one resistor. Only one
pin, VDRIVE, is necessary to support the regulator.
The recommended design for the voltage regulator is shown
in Figure 12. The 10 μF and 100 nF capacitors shown in this
schematic are recommended for bypassing but are not necessary
for operation. Each DVDD pin should have its own 100 nF
bypass capacitor, but only one bulk capacitor (10 μF) is needed
for all pins. In this design, 3.3 V is the main system voltage; 1.8 V
is generated at the collector of the transistor, which is connected
to the DVDD pins. VDRIVE is connected to the base of the PNP
transistor. If the regulator is not used in the design, VDRIVE
can be tied to ground.
3.3V
1k
VDRIVE
DVDD
10F
100nF
ADAU1445/
ADAU1446
+
07
69
6-
0
12
Figure 12. Voltage Regulator Design
Two specifications must be considered when choosing a
regulator transistor. First, the transistor’s current amplification
factor (hFE or beta) should be at least 200. Second, the collector
of the transistor must be able to dissipate the heat generated when
regulating from 3.3 V to 1.8 V. The maximum digital current
draw of the ADAU1445, which uses ASRCs, is 310 mA. The
equation to determine the transistor’s minimum power
dissipation specifications is as follows:
(3.3 V 1.8 V) × 310 mA = 465 mW
Many transistors fit these specifications. Analog Devices
recommends the NJT4030P from On Semiconductor. For
projects with stringent size constraints, an FMMT734 from
Zetex can be used.
The ADAU1446, which does not contain ASRCs, has a lower
maximum digital current draw of approximately 235 mA. The
maximum power dissipation of the transistor in this case should
be around 355 mW.
SRC GROUP DELAY
The group delay of the sample rate converter is dependent on
the input and output sampling frequencies as described in the
following equations.
For fS_OUT > fS_IN,
IN
S
IN
S
f
GDS
_
32
16
+
=
For fS_OUT < fS_IN,
×
+
=
OUT
S
IN
S
IN
S
IN
S
f
GDS
_
32
16
where GDS is the group delay in seconds.
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